Interrupt Taken Debug Event - STMicroelectronics SPC572L series Reference Manual

e200z215An3 Core Debug Support
instruction actually executes and then generates a System Call interrupt. In this case, the
Instruction Complete debug exception will also be set. When an Instruction Complete debug
event is recognized, DBSR
the next instruction to be executed will be recorded in DSRR0.
Instruction Complete debug events are not recognized if MSR
of the instruction, thus DBSR
One circumstance may cause the DBSR
a EFPU Round exception occurs. Since the instruction is by definition completed (SRR0
points to the following instruction), this interrupt takes higher priority than the Debug
interrupt so as not to be lost, and DBSR
Debug interrupt. In this case, the Debug interrupt will be taken with SRR0 pointing to the
instruction following the instruction that generated the EFPU Round exception, and DSRR0
will point to the Round exception handler. In addition to occurring when DBCR0
circumstance can also occur when EDBCR0
which case EDBSR0
Note: Instruction complete debug events are not generated by the execution of an instruction that
sets MSR
DBCR0
ICMP
57.2.7

Interrupt Taken debug event

An Interrupt Taken debug event (IRPT) occurs if Interrupt Taken debug events are enabled
(DBCR0
IRPT
using SRR0/1) cause an Interrupt Taken debug event. This event can occur and be
recorded in DBSR regardless of the setting of MSR
event occurs, the DBSR
DSRR0 will be the address of the non-critical interrupt handler.
57.2.8 Critical Interrupt Taken debug event
A Critical Interrupt Taken debug event (CIRPT) occurs if Critical Interrupt Taken debug
events are enabled (DBCR0
interrupts (an interrupt using CSRR0/1) cause a Critical Interrupt Taken debug event. This
event can occur and be recorded in DBSR regardless of the setting of MSR
Critical Interrupt Taken debug event occurs, the DBSR
debug exception. The value saved in DSRR0 will be the address of the critical interrupt
handler.
57.2.9 Return debug event
A Return debug event (RET) occurs if Return debug events are enabled (DBCR0
and an attempt is made to execute an se_rfi instruction. This event can occur and be
recorded in DBSR regardless of the setting of MSR
the DBSR
If MSR
DE
se_rfi), then DBSR
If MSR
DE
there exists no higher priority exception that is enabled to cause an interrupt. Debug
Save/Restore Register 0 will be set to the address of the se_rfi instruction.
1654/2058
ICMP
IDE
will be set.
IDE
to '1' while DBCR0
DE
to '1' while MSR
DE
=1) and a base-class interrupt occurs. Only base-class interrupts (an interrupt
bit is set to 1 to record the debug exception. The value saved in
IRPT
CIRPT
bit is set to 1 to record the debug exception.
RET
=0 at the time of the execution of the se_rfi (i.e. before the MSR is updated by the
is also set to 1 to record the imprecise debug event.
IDE
=1 at the time of the execution of the se_rfi, a Debug interrupt will occur provided
DocID027809 Rev 4
is set to 1 to record the debug exception and the address of
is not generally set by an ICMP debug event.
and DBSR
ICMP
is set to indicate the imprecise recognition of a
IDE
=1 and the event is hardware-owned, in
EDM
=1, nor by the execution of an instruction that sets
ICMP
=1.
DE
=1) and a critical interrupt occurs. Only critical class
DE
=0 at the time of execution
DE
bits to be set. This occurs when
IDE
. When an Interrupt Taken debug
bit is set to 1 to record the
CIRPT
. When a Return debug event occurs,
RM0400
=1, this
IDM
. When a
DE
=1)
RET