Figure 1006.Once Controller Implementation - STMicroelectronics SPC572L series Reference Manual

e200z215An3 Core Debug Support
Test-Logic-
Reset
1
0
Run - Test /
Idle
0
Access to processor registers and the contents of memory locations are performed by
enabling external debug mode (setting EDBCR0
debug mode, followed by scanning instructions and data into and out of the CPU Scan
Chain (CPUSCR); execution of scanned instructions by the CPU is used as the method to
access required data. Memory locations may be read by scanning a load instruction into the
CPU core, which will reference the desired memory location, executing the load instruction,
and then scanning out the result of the load. Other resources are accessed in a similar
manner.
The initial entry by the CPU into the debug state (or mode) from normal, Waiting, Stopped,
or Halted states (all indicated via the OnCE Status Register (OSR),
Status register) by assertion of one or more debug requests, begins a debug session. The
jd_debug_b output signal indicates that a debug session is in progress, and the OSR will
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Figure 1006. OnCE controller implementation
1
Select DR-
1
Capture - DR
Shift - DR
Exit1 - DR
Pause - DR
Exit2 - DR
0
Update - DR
1
DocID027809 Rev 4
1
Scan
0
0
0
1
1
0
0
1
1
0
to '1'), placing the processor into
EDM
Select - IR
Scan
0
1
Capture - IR
0
Shift - IR
1
Exit1 - IR
0
Pause - IR
1
Exit2 - IR
0
1
Update - IR
1 0
Section 57.5.6.1, OnCE
RM0400
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0
1
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