Test Channel Connection With Internal Analog Channel - STMicroelectronics SPC572L series Reference Manual

RM0400 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Inter-
The sampling phase duration is given by the following equation:
where INPSAMP must be greater than or equal to 5 (hardware requirement). In case the
value of INPSAMP is found to be less than 5, it is automatically set to 5 inside SARADC.
The total evaluation phase duration is given by the following equations:
In this phase, the internal sampling capacitor is disconnected from the analog channel and
ADC estimates the digitized value of the sampled input using successive approximation
algorithm. In the evaluation phase, all the bits are estimated sequentially to provide the
conversion result.
The total conversion duration is (not including external multiplexing) is given by the
following:
The timings refer to the unit t
clock. Total conversion time is < 5µs.
Note: The current implementation of ADCDIG does not support hardware restriction over values of
PRECHG and INPSAMP fields. As minimum values for these fields are product specific and
need to be managed through software.
36.4.4.2 Alternate reference selection
[BLG_SAR_ADC_0007][Covers: ADD22.047]In order to support different accuracy
requirements, a voltage reference can be selected for each channel through REFSEL bit of
the corresponding channel data register (for example, ICDRn). For some channels, this bit
REFSEL is not software programmable and the selection configuration is fixed based on
device-specific requirements.[end]
36.4.5

Test channel connection with internal analog channel

The test channels are meant for monitoring various on-chip analog signals coming from
temperature sensor, bandgap, voltage regulator and different voltage levels available on the
chip. These analog signals can be interfaced to SARADC through test channels for testing
purpose. Test channels are mapped from 96 to 127. Each test channel is controlled in the
same way as normal internal channel.
SAR ADC self-testing method: the test channel[127:124] is also mapped to various V_ref
voltages (4 voltages) selection switches in the ADCBIAS block. The decoding of these
channels to switch on and select a particular V_ref voltage is done in SoC level muxing
logic. Refer ADC configuration for detailed mapping/control description of Self Test feature.
It is also possible to perform test channel conversions with and without shorting the normal
analog channel pin with the internal test voltage. The test channel to internal channel
mapping is enabled through top level synthesis parameter testch_short_intch vector. If
shorting of a particular test channel has to be disabled then the parameter should be set to
'0' for the corresponding test channel. This will result in removal of corresponding TCCAPR
registers (see ADCDig IG for more details on testch_short_intch). For implemented
TCCAPR registers to enable the short between the test channel and any internal analog
channel, ESIC_TCHx bit of TCCAPR0–7 registers should be set. The mapping of the test
t = INPSAMP * t
sample
t = 12 * t
eval ck
t = 10 * t (for 10-bit conversion)
eval ck
t = t + t
conv prechg sample
ck
DocID027809 Rev 4
ck
+ t
eval
refers to reciprocal of f , where f = SARADC peripheral
ck ck
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