STMicroelectronics SPC572L series Reference Manual page 973

RM0400
Offset
TGC1 enable/disable control reg
0x08270 + CCi
(TOM[i]_TGC1_ENDIS_CTRL)
TGC1 enable/disable status reg
0x08274 + CCi
(TOM[i]_TGC1_ENDIS_STAT)
TGC1 output enable control reg
0x08278 + CCi
(TOM[i]_TGC1_OUTEN_CTRL)
TGC1 output enable status reg
0x0827C + CCi
(TOM[i]_TGC1_OUTEN_STAT)
(0x08030 –
0x0803C) +
m*0x0040 + CCi
(0x08400 –
0x087FC) + CCi
0x09000 – 0x0ABFC
0x0AC00 –
0x0CFFC
0x0D000 + ATOM Channel m ARU read address register
m*0x0080 + DDi (ATOM[i]_CH[m]_RDADDR)
0x0D004 + ATOM Channel m control register
m*0x0080 + DDi (ATOM[i]_CH[m]_CTRL)
0x0D008 + ATOM Channel m CCU0 compare shadow
m*0x0080 + DDi register (ATOM[i]_CH[m]_SR0)
0x0D00C + ATOM Channel m CCU1 compare shadow
m*0x0080 + DDi register (ATOM[i]_CH[m]_SR1)
0x0D010 + ATOM Channel m CCU0 compare register
m*0x0080 + DDi (ATOM[i]_CH[m]_CM0)
0x0D014 + ATOM Channel m CCU1 compare register
m*0x0080 + DDi (ATOM[i]_CH[m]_CM1)
0x0D018 + ATOM Channel m CCU0 counter register
m*0x0080 + DDi (ATOM[i]_CH[m]_CN0)
0x0D01C + ATOM Channel m status register
m*0x0080 + DDi (ATOM[i]_CH[m]_STAT)
0x0D020 + ATOM channel m interrupt notification
m*0x0080 + DDi register (ATOM[i]_CH[m]_IRQ_NOTIFY)
0x0D024 + ATOM channel m interrupt enable register
m*0x0080 + DDi (ATOM[i]_CH[m]_IRQ_EN)
0x0D028 + ATOM channel m software interrupt
m*0x0080 + DDi generation (ATOM[i]_CH[m]_IRQ_FORCINT)
0x0D02C + Channel m IRQ mode configuration register
m*0x0080 + DDi (ATOM[i]_CH[m]_IRQ_MODE)
Table 516. GTMINT module memory map(Continued)
Use
ARU-connected Timer Output Module (ATOM) Registers
(DDi = i*0x800, i = 0..2, m = 0..7)
DocID027809 Rev 4
GTM101 Integration (GTMINT) Module
Access
R/W
R/W
R/W
R/W
Reserved (m= 2..7, 10..15)
Reserved
Reserved for TOM2 to TOM5
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(1)
Reset value Location
0x0000_0000 See GTM Spec.
0x0000_0000 See GTM Spec.
0x0000_0000 See GTM Spec.
0x0000_0000 See GTM Spec.
0x01FE_01FE See GTM Spec.
0x0000_X000 See GTM Spec.
0x0000_0000 See GTM Spec.
0x0000_0000 See GTM Spec.
0x0000_0000 See GTM Spec.
0x0000_0000 See GTM Spec.
0x0000_0000 See GTM Spec.
0x0000_0001 See GTM Spec.
0x0000_0000 See GTM Spec.
0x0000_0000 See GTM Spec.
0x0000_0000 See GTM Spec.
0x0000_0000 See GTM Spec.
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
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