STMicroelectronics SPC572L series Manuals

STMicroelectronics SPC572L series Manuals

Manuals and User Guides for STMicroelectronics SPC572L series. We have 1 STMicroelectronics SPC572L series manual available for free PDF download: Reference Manual

STMicroelectronics SPC572L series Reference Manual

STMicroelectronics SPC572L series Reference Manual (2058 pages)

Brand: STMicroelectronics | Category: Microcontrollers | Size: 38 MB

Table of Contents

Table of Contents

2
List of Tables

46
List of Figures

69
- Audience
  91
- Document Organization
  91
- Overview
  91
- Preface
  91
- Register Conventions
  91
- Acronyms and Abbreviations
  92
- Reference Documents
  92
- Core Features
  93
- Introduction
  93
- Memory Hierarchy
  93
- Overall Architecture
  93
- Spc572Lx Microcontroller
  93
- Target Applications
  93
- Features Summary
  95
- Feature List
  96
- Packaging
  97
- Software Debug and Calibration
  97
- Block Diagrams
  98
- Figure 3. Periphery Allocation
  99
- Embedded Memories
  100
- Overlay SRAM
  100
- Overview
  100
- Sram
  100
- System SRAM
  100
- Embedded Flash Memory
  101
- Processor Core Local SRAM
  101
- Flash Memory Array
  102
- Flash Memory Controller
  102
- Security Features
  104
- Package Pinouts
  105
- Pin Descriptions
  105
- Pin Startup and Reset States
  105
- Production Packages
  105
- Signal Description
  105
- Power Supply and Reference Voltage Pins
  106
- System Pins
  106
- LVDS Pins
  107
- Generic Pins
  108
- Memory Map
  109
  - Table 9. Flash Memory and Overlay RAM Map
    113
  - Table 10. RAM Memory Map
    114
- Core Module
  117
- Core Reset Settings
  117
- Device Configuration
  117
- Introduction
  117
- Special Purpose Register (SPR) Summary
  119
- Crossbar Switch Configuration
  122
- SIUL2 Configuration
  122
- System Modules
  122
- System Memory Protection Unit (SMPU) Configuration
  123
- Table 17. Reference Links to Related Information
  124
- Peripheral Bridge Configuration
  125
- Platform Configuration Module (PCM)
  126
- Interrupt Controller (INTC) Configuration
  127
  - Table 22. Interrupt Sources
    128
  - Table 23. Latency Time Categories
    145
- DMA Controller Configuration
  146
- DMACHMUX Configuration
  147
- Table 26. DMAMUX Peripheral DMA Request to Input Source Mapping
  148
- Memories and Memory Interfaces
  150
- Flash Memory Controller (PFLASH) Configuration
  151
- Decorated Storage Memory Controller (DSMC)
  152
- ECC Error Injection Module
  153
- ECC Error Reporting Module
  153
- Analog Modules
  154
- Analog-To-Digital Converters (ADC) Configuration
  154
- Temperature Sensor Configuration
  154
- SARADC Configuration
  155
- SDADC Configuration
  155
- Timers
  155
- Software Watchdog Timer (SWT) Configuration
  156
- System Timer Module (STM) Configuration
  156
- PIT Configuration
  157
- Table 38. Reference Links to Related Information
  158
- Communication Interfaces
  159
- FEC Interface
  159
- GTM Integration Module Configuration
  159
- CAN Nodes
  160
- LFAST and SIPI
  160
- Table 43. Reference Text to Related Information
  161
- DSPI Configuration
  162
  - Table 45. DSPI Instantiation
    163
  - Table 46. DSPI Registers Memory Map
    164
- SENT Receiver (SRX) Configuration
  167
- Linflexd - Configurations
  169
- Linflexd Implemented Registers
  169
- BAF Configuration
  171
- Reset and Boot Modules
  171
- Table 53. Boot Header Structure
  172
- Register Protection (REG_PROT) Configuration
  173
- Safety Modules
  173
- System Status and Configuration Module (SSCM) Configuration
  173
- Password and Device Security Module (PASS) Configuration
  178
- Security Modules
  178
- Debug and Calibration Architecture
  183
- Figure 22. Debug and Calibration Architecture for Spc572Lx
  184
- Boot Assist Flash
  185
- Introduction
  185
- Reset and Boot
  185
- TEST Flash Memory Block
  185
- UTEST Flash Memory Block
  185
- Boot Header
  186
- Modules Used in Reset Sequence
  186
- Power Management Controller
  186
- Reset Generation Module
  186
- Mode Entry Module
  187
- Reset Sequence
  187
- System Status and Configuration Module
  187
- Power-On and the Reset Generation Module
  188
- Power-Up Phase: Power Stabilization
  189
- PHASE0 Phase: Analog Supply Initial Configuration
  190
- PHASE1: Temporization and Monitoring Setup
  191
- PHASE2: Flash Initial Configuration
  191
- PHASE3: Device Configuration
  191
- IDLE Phase
  192
- MC_RGM Passes Boot Sequence Control to the System Status and Control
  193
- Module
  193
- Possible Boot-Up Sequences
  193
- Reset Sequence Flow Based on Initial Device Condition
  193
- Sequence from MC_RGM IDLE to Boot CPU Running Code
  193
- Path from MC_RGM IDLE to Serial Boot Mode
  196
- Path from MC_RGM IDLE with Core Enabled to Watchdog Timer Timeout
  198
- DCF Clients
  205
- Device Configuration Format (DCF) Records
  205
- Introduction
  205
- DCF Records
  206
  - Figure 29. DCF Start Record
    207
  - Table 70. Series of DCF Records in UTEST Flash Memory
    208
- DCF Client Table
  209
- UTEST DCF Records
  209
- DCF Client List
  210
- Miscellaneous DCF Registers
  216
- Overview
  218
- Power Management
  218
- Power Management Framework
  218
- Power Management Supply Description
  219
- Spc572Lx Power Management Controller Overview
  220
- Figure 35. Device High Voltage Power-Ground Network
  221
- Low Power Mode Support
  222
- Low Power Support and STOP Mode Implementation
  223
- Flash Power Requirements
  224
- Behavior of Device Lvds
  225
- Device Trimming
  225
- Power-On Reset (POR)
  225
- Supply Monitoring (por and Lvds)
  225
- Low Voltage Detection (LVD)
  226
  - Table 74. por and Voltage Monitors Description
    227
  - Table 75. Voltage Monitors Configurability
    228
- Power Sequence
  229
- Power-Up Sequence
  230
- Brown-Out Management
  235
- Power-Down Sequence
  235
- Low Voltage Requirement During Crank
  236
- Advanced Security
  237
- Basic Security
  237
- Detailed Security Information
  237
- Security
  237
- Calibration and Debug
  238
- Core Debug Support
  238
- Run Control and Memory Access
  238
- Debug and Calibration Interface (DCI)
  239
- Table 79. DCI_PINCR Register Field Descriptions
  240
- JTAG Data Communication (JDC)
  241
- Sequence Processing Unit (SPU)
  241
- Calibration Interface
  253
- Debug over CAN
  254
- Development Trigger Semaphore (DTS)
  254
- JTAG Master (JTAGM)
  254
- Nexus Aurora
  255
- Nexus Aurora Register Interface Overview
  255
- Nexus Aurora Router (NAR)
  256
- Table 91. PD NAR Clients
  257
- E200Z2 Nexus 3
  258
- Nexus Clients
  258
- Core E200Z215An3 Description
  259
- Overview of the E200Z215An3 Core
  259
- EFPU2 Floating-Point Unit Features
  260
- Register Model
  260
- Register (SPEFSCR)
  264
- Signal Processing Extension/Embedded Floating-Point Status and Control
  264
- Single-Issue Operation
  264
- Exceptions
  266
- Exception Syndrome Register (ESR)
  267
- Table 95. ESR Field Descriptions
  268
- Machine State Register (MSR)
  269
- Machine Check Syndrome Register (MCSR)
  271
- Interrupt Vector Prefix Registers (IVPR)
  273
- Interrupt Definitions
  274
- Introduction
  283
- Overview
  283
- System Integration Unit Lite2 (SIUL2)
  283
- Figure 53. SIUL2 Block Diagram
  284
- Features
  285
- Register Protection
  285
- Memory Map
  286
- Memory Map and Register Description
  286
- Register Descriptions
  287
- Table 113. SIUL2_MIDR1 Field Descriptions
  288
- Table 115. SIUL2_MIDR2 Field Description
  289
- Table 116. SIUL2_DISR0 Field Descriptions
  290
- Table 117. SIUL2_DIRER0 Field Descriptions
  291
- Table 118. SIUL2_DIRSR0 Field Descriptions
  292
- Table 119. SIUL2_IREER0 Field Descriptions
  293
- Table 120. SIUL2_IFEER0 Field Descriptions
  294
- Table 121. SIUL2_IFER0 Field Descriptions
  295
- Table 122. SIUL2_IFMCR0 Field Descriptions
  296
- Figure 64. MSCR I/O Pin and IP Block Port Connectivity
  297
- Table 124. SIUL2_MSCR_IO_0–SIUL2_MSCR_IO_511 Field Description
  298
- Table 125. I/O MSCR Reset State Exceptions
  299
- Table 126. SIUL2_MSCR_MUX_512–SIUL2_MSCR_MUX_1023 Field Description
  300
- Table 127. SIUL2_GPDO0–SIUL2_GPDO511 Field Description
  301
- Table 128. SIUL2_GPDI0–SIUL2_GPDI511 Field Description
  302
- Table 130. SIUL2_PGPDI0 Field Description
  303
- Functional Description
  304
- General
  304
- Pad Control
  304
- General Purpose Input or Output Pads (GPIO)
  305
- External Interrupts/Dma Requests (EIRQ Pins)
  306
- Figure 74. Interrupt to Vector Mapping at MCU Level
  308
- Crossbar Switch (XBAR)
  309
- Features
  309
- Introduction
  309
- Memory Map and Register Definition
  309
- Table 132. XBAR Memory Map
  310
- Table 133. Xbar_Prsn Field Descriptions
  311
- Table 134. Xbar_Crsn Field Descriptions
  313
- Functional Description
  314
- General Operation
  315
- Register Coherency
  315
- Arbitration
  316
- Initialization/Application Information
  317
- Features
  318
- General Operation
  318
- Introduction
  318
- Memory Map and Register Definition
  318
- Peripheral Bridge
  318
- Master Privilege Registers (AIPS_MPRA)
  319
- Peripheral Access Control Registers (Aips_Pacrx)
  320
- Off-Platform Peripheral Access Control Registers (Aips_Opacrx)
  321
- Figure 81. Off-Platform Peripheral Access Control Registers (AIPS_OPACRA–AF)
  323
- Access Support
  324
- Functional Description
  324
- Block Diagram
  325
- Overview
  325
- System Memory Protection Unit (SMPU)
  325
- Figure 83. SMPU Block Diagram
  326
- Features
  327
- Memory Map
  327
- Memory Map and Register Definition
  327
- Table 141. Smpux Memory Map
  328
- Register Descriptions
  331
- Table 143. SMPU0_CESR1 Field Descriptions
  332
- Table 144. Smpu0_Earn Field Descriptions
  333
- Table 145. Smpu0_Edrn Field Descriptions
  334
- Table 147. Smpu0_Rgdn_Word1 Field Descriptions
  335
- Table 148. Smpu0_Rgdn_Word2_Fmt0 Field Descriptions
  336
- Figure 91. Region Descriptor N, Word 2 Format 1 (Smpu0_Rgdn_Word2_Fmt1)
  337
- Table 149. Smpu0_Rgdn_Word2_Fmt1 Field Descriptions
  338
- Table 150. Smpu0_Rgdn_Word3 Field Descriptions
  339
- Access Evaluation Macro
  340
- Functional Description
  340
- Figure 93. SMPU Access Evaluation Macro
  341
- Application Information
  342
- Initialization Information
  342
- Putting It All Together and Error Terminations
  342
- Table 152. Overlapping Region Descriptor Example
  343
- Intelligent AHB Gasket (IAHBG)
  345
- Introduction
  345
- Timing Diagrams
  345
- Figure 100. Burst4 Read (2:1 Timing Mode)
  350
- Figure 101. Burst4 Write (2:1 Timing Mode)
  351
- Figure 102. Read, Pending Read (1:2 Timing Mode)
  352
- Figure 103. Write, Pending Read (1:2 Timing Mode)
  353
- Figure 104. Burst4 Read (1:2 Timing Mode)
  354
- 32 Interface
  355
- Block Diagram
  357
- Interrupt Controller (INTC)
  357
- Introduction
  357
- Figure 106. Block Diagram for an INTC with Four Processors
  358
- Features
  359
- Modes of Operation
  359
- Software Vector Mode
  359
- Hardware Vector Mode
  360
- Memory Map
  360
- Memory Map and Register Definition
  360
- Register Descriptions
  361
- Table 155. INTC_BCR Field Descriptions
  362
- Table 156. Intc_Cprn Field Descriptions
  363
- Table 157. Intc_Iackrn Field Descriptions
  364
- Table 159. Intc_Sscirn Field Descriptions
  365
- Table 160. Intc_Psrn Field Descriptions
  366
- Functional Description
  367
- Interrupt Request Sources
  367
- Priority Management
  368
- Handshaking with Processor
  369
- Figure 114. Timing Diagram of Software Vector Mode Handshaking
  371
  - Initialization/Application Information
    372
- Interrupt Exception Handler
  373
- ISR, RTOS, and Task Hierarchy
  375
- Table 162. Order of ISR Execution Example
  376
- Priority Ceiling Protocol
  377
- Figure 116. Interrupt Request Block Diagram
  378
- Selecting Priorities According to Request Rates and Deadlines
  379
- Software-Settable Interrupt Requests
  380
- Negating an Interrupt Request Outside of Its ISR
  381
- Interrupt Sources
  382
  - Introduction
    383
  - Modes of Operation
    384
- Wait Mode
  385
- Control Register (DMA_CR)
  397
- Table 165. DMA_CR Field Descriptions
  398
- Error Status Register (DMA_ES)
  399
- Enable Request Register Low (DMA_ERQL)
  400
- Table 167. DMA_ERQL Field Descriptions
  401
- Enable Error Interrupt Register Low (DMA_EEIL)
  402
- Table 168. DMA_EEIL Field Descriptions
  403
- Set Enable Request Register (DMA_SERQ)
  404
- Clear Enable Request Register (DMA_CERQ)
  405
- Clear Enable Error Interrupt Register (DMA_CEEI)
  406
- Clear Interrupt Request Register (DMA_CINT)
  407
- Set START Bit Register (DMA_SSRT)
  408
- Interrupt Request Register Low (DMA_INTL)
  409
- Table 177. DMA_INTL Field Descriptions
  410
- Error Register Low (DMA_ERRL)
  411
- Table 178. DMA_ERRL Field Descriptions
  412
- Hardware Request Status Register Low (DMA_HRSL)
  413
- Table 179. DMA_HRSL Field Descriptions
  414
- Channel N Priority Register (Dma_Dchprin)
  415
- TCD Source Address (Dma_Tcdn_Saddr)
  416
- TCD Transfer Attributes (Dma_Tcdn_Attr)
  417
- TCD Signed Source Address Offset (Dma_Tcdn_Soff)
  418
- Table 185. Dma_Tcdn_Nbytes_Mlno Field Descriptions
  419
- TCD Last Source Address Adjustment (Dma_Tcdn_Slast)
  421
- TCD Destination Address (Dma_Tcdn_Daddr)
  422
  - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (Dma_Tcdn_Citer_Elinkno)
    423
- TCD Signed Destination Address Offset (Dma_Tcdn_Doff)
  424
  - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (Dma_Tcdn_Biter_Elinkyes)
    425
  - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (Dma_Tcdn_Biter_Elinkno)
    426
- TCD Control and Status (Dma_Tcdn_Csr)
  427
- Table 195. Dma_Tcdn_Csr Field Descriptions
  428
  - Functional Description
    429
- Edma Basic Data Flow
  430
- Figure 151. DMA Operation, Part 1
  431
- Figure 152. DMA Operation, Part 2
  432
- Error Reporting and Handling
  433
- Channel Preemption
  435
- Table 197. Edma Peak Request Rate (Mreq/S)
  437
  - Initialization/Application Information
    438
- Table 198. TCD Control and Status Fields
  439
- DMA Programming Errors
  440
- DMA Transfer
  441
- Edma Tcdn Status Monitoring
  444
- Table 201. TCD Status Sequence – Hardware Activated Channel
  445
- Channel Linking
  446
- Dynamic Programming
  447
- Table 204. Coherency Model for Method 1
  448
- Table 205. Coherency Model for Method 2
  449
- Direct Memory Access Multiplexer (DMAMUX)
  450
  - Features
    451
- Channel Configuration Register (Dmamux_Chcfgn)
  452
  - Functional Description
    453
- Figure 158. DMAMUX Triggered Channels
  454
- DMA Channels with no Triggering Capability
  455
  - Initialization/Application Information
    456
- Clocking
  461
- Figure 161. Clock Generation
  462
- MC_CGM Registers
  463
- JTAG Frequencies
  464
- Clock Sources
  465
- Table 211. PLL Register Write Protection
  466
- External Oscillator (XOSC)
  467
- Mhz Internal RC Oscillator (IRCOSC)
  468
- Peripheral Clocks
  469
- LFAST Clocking
  470
- Table 216. LFAST and Ethernet Use Cases
  471
- Ethernet Clocking
  472
- Sigma-Delta ADC Clocking
  473
- Clock Monitoring
  474
- Table 217. Clock Input Sources
  475
- PLL0 Monitor
  476
- Loss of System Clock Behavior
  477
- PLL Digital Interface (PLLDIG)
  478
  - Memory Map and Register Definition
    479
- Table 221. PLLCR Field Descriptions
  480
- Table 222. PLLSR Field Descriptions
  481
- Table 223. PLLDV Field Descriptions
  482
  - Register Classification for Safety Requirements
    483
- Clock Configuration
  484
- Loss of Lock
  485
- Clock Monitor Unit (CMU)
  486
- Signals
  487
  - Memory Map and Register Definition
    488
- Table 226. CMU_CSR Field Descriptions
  489
- Table 227. CMU_FDR Field Descriptions
  490
- Table 229. CMU_LFREFR Field Descriptions
  491
- Table 230. CMU_ISR Field Descriptions
  492
  - Functional Description
    493
- Clock Generation Module (MC_CGM)
  495
- Figure 180. Mc_Cgmblock Diagram
  496
  - Features
    497
  - Register Descriptions
    499
- Table 233. PCS Switch Duration Register (CGM_PCS_SDUR) Field Descriptions
  500
- Table 235. PCS Divider Start Register 1 (CGM_PCS_DIVS1) Field Descriptions
  501
- Table 237. PCS Divider Change Register 2 (CGM_PCS_DIVC2) Field Descriptions
  502
- Table 238. PCS Divider Start Register 2 (CGM_PCS_DIVS2) Field Descriptions
  503
- Table 240. PCS Divider Change Register 3 (CGM_PCS_DIVC3) Field Descriptions
  504
- Table 241. PCS Divider Start Register 3 (CGM_PCS_DIVS3) Field Descriptions
  505
- Table 243. System Clock Select Status Register (CGM_SC_SS) Field Descriptions
  506
- Table 244. System Clock Divider 0 Configuration Register (CGM_SC_DC0) Field Descriptions
  507
- Table 245. System Clock Divider 1 Configuration Register (CGM_SC_DC1) Field Descriptions
  508
- Table 246. Auxiliary Clock 0 Select Control Register (CGM_AC0_SC) Field Descriptions
  509
- Table 247. Auxiliary Clock 0 Select Control Register (CGM_AC0_SC) Field Descriptions
  510
- Table 249. Auxiliary Clock 0 Divider 1 Configuration Register (CGM_AC0_DC1) Field Descriptions
  511
- Table 250. Auxiliary Clock 0 Divider 2 Configuration Register (CGM_AC0_DC2) Field Descriptions
  512
- Table 251. Auxiliary Clock 1 Select Control Register (CGM_AC1_SC) Field Descriptions
  513
- Table 252. Auxiliary Clock 1 Select Status Register (CGM_AC1_SS) Field Descriptions
  514
- Table 254. Auxiliary Clock 2 Divider 0 Configuration Register (CGM_AC2_DC0) Field Descriptions
  515
- Table 255. Auxiliary Clock 3 Select Control Register (CGM_AC3_SC) Field Descriptions
  516
- Table 256. Auxiliary Clock 3 Select Status Register (CGM_AC3_SS) Field Descriptions
  517
- Table 257. Auxiliary Clock 7 Select Control Register (CGM_AC7_SC) Field Descriptions
  518
- Table 258. Auxiliary Clock 7 Select Status Register (CGM_AC7_SS) Field Descriptions
  519
- Table 259. Auxiliary Clock 7 Divider 0 Configuration Register (CGM_AC7_DC0) Field Descriptions
  520
- Table 260. Auxiliary Clock 8 Select Control Register (CGM_AC8_SC) Field Descriptions
  521
- Table 261. Auxiliary Clock 8 Select Status Register (CGM_AC8_SS) Field Descriptions
  522
- Table 262. Auxiliary Clock 8 Divider 0 Configuration Register (CGM_AC8_DC0) Field Descriptions
  523
- Table 263. Auxiliary Clock 10 Select Control Register (CGM_AC10_SC) Field Descriptions
  524
- Table 264. Auxiliary Clock 10 Select Status Register (CGM_AC10_SS) Field Descriptions
  525
- Figure 214. Auxiliary Clock 11 Select Control Register (CGM_AC11_SC)
  526
- Table 266. Auxiliary Clock 11 Select Control Register (CGM_AC11_SC) Field Descriptions
  527
- Table 267. Auxiliary Clock 11 Select Status Register (CGM_AC11_SS) Field Descriptions
  528
- Figure 217. Auxiliary Clock 11 Divider 1 Configuration Register (CGM_AC11_DC1)
  529
  - Functional Description
    530
- Table 270. MC_CGM Cgm_Pcs_Divcn[Rate] Values
  531
- Figure 218. MC_CGM System Clock Ramp-Down Timing (K = 6 Example)
  532
- Tion
  533
- Tion
  534
- Auxiliary Clock Generation
  535
- Figure 221. MC_CGM Auxiliary Clock 1 Generation Overview
  536
- Figure 223. MC_CGM Auxiliary Clock 3 Generation Overview
  537
- Figure 225. MC_CGM Auxiliary Clock 8 Generation Overview
  538
- Figure 227. MC_CGM Auxiliary Clock 11 Generation Overview
  539
- Dividers Functional Description
  540
- Figure 228. MC_CGM Fractional Division Example Waveform (Divide by 2.3)
  541
- OSC Digital Interface (XOSC)
  542
- Oscillator Startup Delay
  543
  - Register Descriptions
    544
- IRCOSC Digital Interface
  546
  - Register Descriptions
    547
- Table 279. IRCOSC_NT Field Descriptions
  548
- Table 280. IRCOSC_TT Field Descriptions
  549
- RAM Controller (PRAM)
  550
  - Memory Map and Register Definition
    551
- SRAM ECC Mechanism
  552
- Figure 238. PFLASH_MP55 Block Diagram
  557
- Flash Memory Controller Memory Map
  558
- Figure 239. PFCR1 Register
  559
- Table 284. PFCR1 Field Descriptions
  560
- Figure 241. PFCR3 Register
  563
- Table 285. PFCR3 Field Descriptions
  564
- Table 286. PFAPR Field Descriptions
  565
- Table 287. PFCRCR Field Descriptions
  568
- Table 288. PFCRDE Field Descriptions
  569
- Table 289. Pflash Calibration Region Descriptor N, Word 0 Description
  576
- Table 290. Pflash Overlay Region Descriptor N, Word 1 Description
  577
- Table 291. Pflash Overlay Region Descriptor N, Word 2 Description
  578
  - Functional Description
    579
- Read Cycles - Buffer Miss
  580
- Censorship
  581
- Instruction/Data Prefetch Triggering
  582
- Table 292. Calibration Data Memory Base Addresses
  583
- Figure 250. Pflash Calibration Remap Logic Detail
  585
- Safety Considerations
  587
- Figure 252. Safety-Critical Calibration Remap Datapath with Redundancy
  589
- Array Integrity Considerations
  590
  - Embedded Flash Memory (MP55)
    591
- Figure 253. Flash Memory Module Structure
  592
  - Features
    593
- Flash Memory Map and Description
  594
- Flash Array Memory Map
  595
- Table 295. Testflash Block Memory Map
  596
- Register Memory Maps and Descriptions
  597
- Register Memory Maps
  598
- User Register Descriptions
  599
- Table 298. MCR Field Descriptions
  600
- Table 299. MCR Bits Set/Clear Priority Levels
  607
- Table 301. LOCK0 Field Descriptions
  610
- Table 302. LOCK1 Field Descriptions
  612
- Table 303. LOCK2 Field Descriptions
  613
- Table 304. SEL0 Field Descriptions
  614
- Table 305. SEL1 Field Descriptions
  615
- Table 306. SEL2 Field Descriptions
  616
- Table 307. ADR Update Mode List
  617
- Table 310. Flash Memory Partition 0 Addresses Mapping
  618
- Table 311. Flash Memory Partition 1 Addresses Mapping
  619
- Table 313. UM0 Field Descriptions
  622
- Table 315. UM2 Field Descriptions
  623
- Table 317. UM8 Field Descriptions
  624
- Table 319. OPP0 Field Descriptions
  625
- Figure 271. Over-Program Protection 1 Register (OPP1)
  626
- Table 320. OPP1 Field Descriptions
  627
- Table 321. OPP2 Field Descriptions
  628
  - Functional Description
    629
- Low-Power Mode (Sleep Mode)
  630
- Read Mode
  631
- Table 323. Bits Manipulation: Doublewords with the same ECC Value
  632
- Modify Mode
  633
- Protection Strategy
  643
- Table 325. Test Mode Disable Block Select
  644
  - Decorated Storage Memory Controller (DSMC)
    645
- DSMC Block Diagram
  646
- Figure 275. DSMC Block Diagram
  647
- Decorated Stores: St[B,H,W]D{Cb}X Rs,Rb,Ra
  648
- Figure 277. Decoration Format: CAST
  650
- Figure 279. Decoration Format: or
  651
- Figure 281. Decoration Format: SLD
  652
- DSMC Timing Diagram
  653
- DSMC Instantiations
  654
- Flash Memory Programming and Configuration
  655
- Selection of Flash Memory Blocks for Erase
  656
- Table 326. Sample Low and MID Address Space Flash Block Bit Mapping
  657
- Non-Secure Write Protection
  658
- Secure Write Protection
  659
- Implementing Secure Write Protection
  661
- Figure 289. DCF Record Structure
  662
- Figure 290. Sample DCF Record for Secure Write Protection
  663
- Overriding Secure Write Protection
  664
- Figure 291. Lock0_Pgn Register
  665
- Secure Read Protection
  666
- Implementing Secure Read Protection
  667
- Table 327. Sample Low and MID Address Space Flash Block Bit Mapping
  668
- Overriding Secure Read Protection
  669
- Debug Port Enable/Disable
  670
- Unconditional Test Mode Disable Seal
  671
- Selecting Flash Memory Blocks for Test Mode Disable Seal
  672
- Planning Secure Write Protection
  673
- Error Reporting Module (ERM)
  674
  - Register Descriptions
    675
- Table 329. ERM_CR Field Descriptions
  676
- Table 330. ERM_SR Field Descriptions
  678
- Table 331. Erm_Earn Field Description
  681
  - Functional Description
    682
- Error Injection Module (EIM)
  683
  - Features
    684
  - Register Descriptions
    685
- Table 334. Error Injection Module Configuration Register (EIMCR) Field Description
  686
- Table 335. Error Injection Channel Enable Register (EICHEN) Field Description
  687
- Table 336. Error Injection Channel N Descriptor, Word0 (Eichdn.word0) Field Description
  689
  - Functional Description
    690
- Analog-To-Digital Converter (ADC) Configuration
  692
- Analog Input Pin Multiplexing
  693
- Configuration of ADC Modules
  694
- Table 340. Sigma-Delta ADC External Signal Description
  695
- Figure 304. Sigma-Delta ADC Integration Diagram
  696
- Figure 305. Sigma-Delta ADC Clock Diagram
  697
- Figure 306. Sigma-Delta ADC External Modulator Interface
  698
- Table 341. Register Fields for SD ADC Analog Input Channel Selection
  699
- Table 342. SD ADC3 Analog Input An[X] Selection
  700
- Table 343. SAR ADC External Signal Description
  701
- Figure 307. SAR ADC Integration Diagram
  702
- Figure 308. SAR ADC Clock Diagram
  703
- Table 344. SAR ADC Alternate References
  704
- Figure 310. Self Test Implementation
  705
- Figure 311. Analog Input Pin Pull Up/Down Pad Cell
  706
- Table 345. SAR ADC Analog Input Channel Assignment
  707
- Table 346. SARB Analog Test Channel Assignment
  708
- Table 347. SAR ADC Register Descriptions
  709
- Table 348. SAR ADC Test Channel Register Descriptions (SARB Only)
  710
- Table 350. SAR ADCB Register Definitions
  711
- Table 351. SAR ADCB Test Channel Register Definitions
  718
- Table 352. SAR ADCB External Channel Register Definitions
  722
- Table 353. SAR ADC0 Register Definitions
  725
- Table 354. SAR ADC4 Register Definitions
  728
- Sigma-Delta Analog-To-Digital Converter (SDADC) Digital Interface
  732
- Figure 314. SDADC Block Diagram
  733
  - Features
    734
  - External Signal Description
    735
  - Memory Map and Register Descriptions
    736
- Table 358. MCR Field Descriptions
  737
- Table 359. CSR Field Descriptions
  740
- Table 360. Analog Input AN[0:7] Selection
  741
- Table 361. RKR Field Descriptions
  742
- Table 362. SFR Field Descriptions
  743
- Table 363. RSER Field Descriptions
  744
- Figure 320. Output Settling Delay Register (OSDR)
  745
- Table 364. OSDR Field Descriptions
  746
- Figure 322. Software Trigger Key Register (STKR)
  747
  - Functional Description
    748
- Differential Input Mode
  749
- Programmable Gain and Decimation Rate
  750
- Hardware Triggering
  751
- Interrupt/Dma Request Support
  752
- Offset Calibration Support
  753
- Data Conversion Step
  754
  - Introduction
    756
- Figure 324. SARADC Block Diagram
  757
  - Feature Description
    758
- Figure 325. Normal Conversion Flow
  759
- Injected Channel Conversion
  760
- Abort Conversion
  761
- Analog Conversion Timings and Reference Selection
  762
- Test Channel Connection with Internal Analog Channel
  763
- Programmable Analog Watchdog
  764
- DMA Functionality
  765
- Power down Mode
  766
- Table 369. SARADC Digital Interface Register Map
  767
  - Register Descriptions
    769
- Figure 330. Main Status Register (MSR)
  771
- Table 371. MSR Field Descriptions
  772
- Table 372. ISR Field Descriptions
  773
- Table 373. ICIPR0–ICIPR2 Field Descriptions
  774
- Table 375. IMR Field Descriptions
  775
- Table 376. ICIMR0–ICIMR2 Field Descriptions
  776
- Table 378. WTISR Field Descriptions
  777
- Table 379. WTIMR Field Descriptions
  778
- Table 380. DMAE Register Field Descriptions
  779
- Table 381. ICDSR0–ICDSR2 Field Descriptions
  780
- Table 384. CTR0–CTRL3 Field Descriptions
  781
- Table 385. ICNCMR0–ICNCMR2 Field Descriptions
  782
- Table 387. ICJCMR0–ICJCMR2 Field Descriptions
  783
- Table 389. PDEDR Field Descriptions
  784
- Table 390. ICDR0–ICDR95 Field Descriptions
  785
- Figure 345. Watchdog Threshold Registers 4–15 (WTHRHLR4–WTHRHLR15)
  786
- Table 391. WTHRHLR4–WTHRHLR15 Field Descriptions
  787
- Table 393. Internal Channel Watchdog Enable Registers to Channel Association
  788
- Table 396. ICAWORR0–ICAWORR2 Field Descriptions
  789
- Table 398. TCIPR Field Descriptions
  790
- Table 400. TCIMR Field Descriptions
  791
- Table 402. TCDSR Field Descriptions
  792
- Table 404. TCNCMR Field Descriptions
  793
- Table 408. TCWSELR0–TCWSELR3 Field Descriptions
  794
- Table 410. TCWENR Field Descriptions
  795
- Table 412. TCAWORR Field Descriptions
  796
- Scriptions
  797
- Table 416. TCDR96–TCDR127 Field Descriptions
  799
- Start of Conversion Pulse Delay
  800
- Table 417. Start of Conversion Pulse Delay Table
  801
  - Initialization Information
    802
  - Introduction
    804
- Figure 359. Decimation Filter Block Diagram
  805
  - Features
    806
  - External Signal Description
    807
- Decimation Filter Device Memory Map
  808
- Decimation Filter Register Descriptions
  809
- Table 420. DECFILTER_MCR Field Descriptions
  810
- Table 421. DECFILTER_MCR Field Descriptions
  813
- Table 422. DECFILTER_MXCR Field Descriptions
  816
- Figure 363. Decimation Filter Extended Status Register (DECFILTER_MXSR)
  818
- Table 423. DECFILTER_MXSR Field Descriptions
  819
- Table 424. DECFILTER_IB Field Descriptions
  821
- Table 425. DECFILTER_OB Field Descriptions
  822
- Table 426. Decfilter_Coefn Field Descriptions
  823
- Table 428. DECFILTER_FINTVAL Field Descriptions
  824
- Table 429. DECFILTER_FINTCNT Field Descriptions
  825
  - Functional Description
    826
- Data Interface Sub-Block Description
  827
- Output Buffer Description
  828
- IIR and FIR Filter
  829
- Figure 373. Fourth Order IIR Filter Implementation Block Diagram
  830
- Figure 374. Filter Configuration Paths (FIR or 1X4Poles IIR)
  831
- Filter Prefill Control Description
  832
- Soft Reset Command Description
  833
  - Interrupts Requests Description
    834
- DMA Requests Description
  835
- Integrator
  836
  - Initialization Information
    839
- Filter Example Simulation
  840
- Input Data Calculation
  841
  - Temperature Sensor
    842
- Linear Temperature Sensor (Analog Output Generation)
  843
- Temperature Formula
  844
- Calculating Device Temperature
  845
- System Timer Module (STM)
  846
  - Register Descriptions
    847
- Table 435. STM_CR Field Descriptions
  848
- Table 437. Stm_Ccrn Field Descriptions
  849
  - Functional Description
    850
- Software Watchdog Timer (SWT)
  851
  - Register Descriptions
    852
- Table 441. SWT_CR Field Descriptions
  853
- Table 442. SWT_IR Field Descriptions
  854
- Table 443. SWT_TO Field Descriptions
  855
- Table 445. SWT_SR Field Descriptions
  856
  - Functional Description
    857
- Figure 391. Pseudorandom Key Generator
  858
- Periodic Interrupt Timer (PIT)
  859
  - Features
    860
- Figure 393. PIT Module Control Register (Pitx_Mcr)
  861
- Table 449. Pitx_Mcr Field Descriptions
  862
- Table 451. Pitx_Ltmr64L Field Descriptions
  863
- Table 453. Pitx_Cvaln Field Descriptions
  864
- Table 454. Pitx_Tctrln Field Descriptions
  865
  - Functional Description
    866
- Interrupts
  867
- Example Configuration for Chained Timers
  868
- Example Configuration for the Lifetime Timer
  869
- GTM Development Interface (GTMDI)
  870
  - Overview
    871
- Figure 404. GTMDI and GTM Interface
  872
- Table 456. GTM Sub-Module Instances
  873
- Figure 405. Watchpoint Triggers and Watchpoint Messages
  874
  - Features
    875
  - Modes of Operation
    876
- Event in (EVTI)
  877
- Test Mode Select (TMS)
  878
  - Register Descriptions
    880
- Table 459. DID Field Descriptions
  881
- Table 460. GTMDI_DC Field Descriptions
  882
- Table 461. GTMDI_DS Field Descriptions
  884
- Table 462. GTMDI_TIM_WPC1 Field Descriptions
  886
- Table 463. GTMDI_TIM_WPC2 Field Descriptions
  888
- Table 464. GTMDI_TOM_WPC1 Field Descriptions
  890
- Figure 412. TOM Watchpoint Control 2 Register (GTMDI_TOM_WPC2)
  892
- Table 465. GTMDI_TOM_WPC2 Field Descriptions
  893
- Figure 413. ATOM Watchpoint Control 1 Register (GTMDI_ATOM_WPC1)
  894
- Table 466. GTMDI_ATOM_WPC1 Field Descriptions
  895
- Table 467. GTMDI_ATOM_WPC2 Field Descriptions
  897
- Table 468. GTMDI_SPEA_WPC1 Field Descriptions
  899
- Figure 416. SPEA Watchpoint Control 2 Register (GTMDI_SPEA_WPC2)
  900
- Table 469. GTMDI_SPEA_WPC2 Field Descriptions
  901
- Figure 417. SPEB Watchpoint Control 1 Register (GTMDI_SPEB_WPC1)
  902
- Table 470. GTMDI_SPEB_WPC1 Field Descriptions
  903
- Table 471. GTMDI_SPEB_WPC2 Field Descriptions
  904
- Table 472. GTMDI_DPLL_WPC1 Field Descriptions
  906
- Figure 420. DPLL Watchpoint Control 2 Register (GTMDI_DPLL_WPC2)
  907
- Table 473. GTMDI_DPLL_WPC2 Field Descriptions
  908
- Table 474. GTMDI_DPLL_WPC3 Field Descriptions
  909
- Table 475. GTMDI_DPLL_WPC4 Field Descriptions
  910
- Table 476. GTMDI_DPLL_WPC5 Field Descriptions
  911
- Figure 425. ARU Watchpoint Control 1 Register (GTMDI_ARU_WPC1)
  912
- Table 478. GTMDI_ARU_WPC1 Field Descriptions
  913
- Table 479. GTMDI_ARU_WPC2 Field Descriptions
  914
- Figure 427. ARU Watchpoint DATA0H Register (GTMDI_ARU_DATA0H)
  915
- Table 480. GTMDI_ARU_DATA0H Field Descriptions
  916
- Table 482. GTMDI_ARU_DATA1H Field Descriptions
  917
- Table 484. GTMDI_ARU_DTC Field Descriptions
  918
- Table 485. GTMDI_MCSA_DC and GTMDI_MCSB_DC Field Descriptions
  920
- Table 486. GTMDI_MCSA_WPC and GTMDI_MCSB_WPC Field Descriptions
  921
- Table 487. GTMDI_MCSA_PTC and GTMDI_MCSB_PTC Field Descriptions
  923
- Table 488. GTMDI_MCSA_DTC and GTMDI_MCSB_DTC Field Descriptions
  924
- Table 489. GTMDI_MCSA_WPA1 and GTMDI_MCSB_WPA1 Field Descriptions
  925
- Table 490. GTMDI_MCSA_WPA2 and GTMDI_MCSB_WPA2 Field Descriptions
  926
- Table 491. GTMDI_MCSA_WPD1 and GTMDI_MCSB_WPD1 Field Descriptions
  927
- Table 493. GTMDI_MCSA_CE and GTMDI_MCSB_CE Field Descriptions
  928
- Table 494. GTMDI_MCSA_DTAR1 and GTMDI_MCSB_DTAR1 Field Descriptions
  930
- Table 495. GTMDI_MCSA_DTAR2 and GTMDI_MCSB_DTAR2 Field Descriptions
  931
- Table 496. GTMDI_TBU0_WPC1 Field Descriptions
  932
- Table 497. GTMDI_TBU0_WPC2 Field Descriptions
  933
- Figure 445. TBU0 Watchpoint DATA Register (GTMDI_TBU0_DATA)
  934
- Table 498. GTMDI_TBU0_DATA Field Descriptions
  935
- Figure 447. TBU1 Watchpoint Control 2 Register (GTMDI_TBU1_WPC2)
  936
- Table 500. GTMDI_TBU1_WPC2 Field Descriptions
  937
- Table 501. GTMDI_TBU1_DATA Field Descriptions
  938
- Table 502. GTMDI_TBU2_WPC1 Field Descriptions
  939
- Figure 450. TBU2 Watchpoint Control 2 Register (GTMDI_TBU2_WPC2)
  940
- Table 503. GTMDI_TBU2_WPC2 Field Descriptions
  941
- Unimplemented Registers
  942
- Debug Enable Logic
  943
- GTMDI Reset Configuration
  944
  - Message Data Bus —Interface with NAR Module
    945
- Table 506. Debug Status Field Format
  947
- Table 509. Watchpoint Field WPHIT[11:0] Format for WPHIT[14:12] = 0B001
  948
- IEEE 1149.1 (JTAG) Input Port
  949
- Table 512. Implemented Instructions
  950
- Figure 455. IEEE 1149.1 16-State Finite State Machine
  951
- Table 513. Loading NEXUS-ENABLE Instruction
  952
- Table 514. Writing to a Register
  953
- Nexus Class 1 Development Support
  954
- Figure 460. Data Write Message Format
  955
- Figure 462. GTMDI Generic Data Trace Flow Diagram
  956
- Fetch Trace
  957
- Figure 464. Fetch Trace State Machine State Diagram
  958
- Watchpoint Trace
  959
  - Introduction
    961
  - Modes of Operation
    963
  - Memory Map and Register Definition
    964
- Table 516. GTMINT Module Memory Map
  966
  - Register Descriptions
    984
- Table 518. GTMINTCLR Field Descriptions
  985
  - Functional Description
    987
- Table 521. Submodules of GTM-IP
  988
- GTMDI Debug Interface
  989
- Table 522. ECC Characteristics for GTM Memories
  990
- Table 523. 42 Bits Word Based Syndrome Definition
  991
- Stop Mode Description
  992
- Debug / Halt Mode Description
  993
  - Initialization/Application Information
    994
  - Introduction
    996
  - Features
    997
- Modular CAN Cores
  998
  - Features
    999
- Block Diagram
  1000
- Dual Clock Sources
  1001
- Table 525. M_CAN Memory Map
  1002
- Table 526. Core Release Register Field Descriptions
  1004
- Table 527. Endian Register Field Descriptions
  1005
- Table 528. Fast Bit Timing and Prescaler Register
  1006
- Table 529. Test Register Field Descriptions
  1007
- Table 530. RAM Watchdog Register Field Descriptions
  1008
- Table 532. Bit Timing and Prescaler Field Descriptions
  1011
- Table 533. Timestamp Counter Configuration Field Descriptions
  1012
- Table 534. Timeout Counter Configuration Field Descriptions
  1013
- Table 535. Timeout Counter Value Field Descriptions
  1014
- Table 536. Error Counter Register Field Descriptions
  1015
- Table 537. PSR Descriptions
  1016
- Table 538. Interrupt Register Field Descriptions
  1018
- Table 539. Interrupt Enable Register Field Descriptions
  1021
- Table 540. Interrupt Line Select Register Field Descriptions
  1024
- Figure 488. Interrupt Line Enable Register
  1026
- Table 541. Interrupt Line Enable Register Field Descriptions
  1027
- Table 543. Standard ID Filter Configuration Register Field Descriptions
  1028
- Table 544. Extended ID Filter Configuration Register Field Descriptions
  1029
- Table 545. Extended ID and Mask Register Field Descriptions
  1030
- Table 546. High Priority Message Status Register Field Descriptions
  1031
- Table 548. NDAT2 Register Field Descriptions
  1032
- Table 549. Rx FIFO 0 Configuration Register Field Descriptions
  1033
- Table 552. Rx FIFO 0 Acknowledge Register Field Descriptions
  1034
- Table 553. Rx FIFO 0 Configuration Register Field Descriptions
  1035
- Table 554. Rx FIFO 0 Configuration Register Field Descriptions
  1036
- Table 556. Rx FIFO 1 Acknowledge Register Field Descriptions
  1037
- Table 557. Tx Buffer Configuration Register Field Descriptions
  1038
- Table 558. Tx Buffer Configuration Register Field Descriptions
  1039
- Table 559. Tx Buffer Request Pending Register Field Descriptions
  1040
- Table 560. Tx Buffer Add Request Register Field Descriptions
  1041
- Table 561. TXBCR Field Descriptions
  1042
- Table 563. Tx Buffer Cancellation Finished Field Description
  1043
- Table 564. Tx Buffer Transmission Interrupt Field Description
  1044
- Table 566. Tx Event FIFO Configuration Field Description
  1045
- Message RAM
  1046
- Figure 514. Message RAM Configuration
  1047
- Table 569. Rx FIFO Element Descriptions
  1048
- Table 570. Tx Buffer Element Descriptions
  1049
- Table 571. Tx Event FIFO Element
  1050
- Table 572. Standard Message ID Filter Element Field Description
  1051
- Figure 519. Extended Message ID Filter Element
  1052
- Table 573. Extended Message ID Filter Element Field Description
  1053
- M_CAN Functional Description
  1054
- Table 574. Coding of DLC in CAN FD
  1058
- Figure 520. Transceiver Delay Measurement
  1059
- Figure 521. Pin Control in Bus Monitoring Mode
  1060
- Timestamp Generation
  1062
- Timeout Counter
  1063
- Figure 524. Standard Message ID Filter Path
  1065
- Figure 525. Extended Message ID Filter Path
  1066
- Dedicated Rx Buffers
  1067
- Debug on CAN Support
  1068
- Tx Handling
  1069
- Figure 527. Example of Mixed Configuration Dedicated Tx Buffers / Tx FIFO
  1071
- FIFO Acknowledge Handling
  1072
- Interface to DMA Controller
  1073
- Figure 530. Connection of Clock Calibration on CAN Unit to M_CAN
  1074
- Figure 531. Bypass Operation
  1075
- Table 577. Clock Calibration on CAN Register Map
  1076
- Table 578. Tx Core Release Register Field Descriptions
  1077
- Table 580. Calibration Configuration Register Field Descriptions
  1078
- Table 581. Calibration Status Register Field Descriptions
  1079
- Table 582. Calibration Status Register Field Descriptions
  1080
- Table 583. CU Interrupt Register Field Descriptions
  1081
- Table 584. CU Interrupt Enable Register Field Descriptions
  1082
- Figure 538. Calibration FSM
  1083
- Table 585. Calibration on CAN Module Interface
  1085
- CAN RAM Arbiter
  1086
- Functional Overview Using Examples
  1087
- ECC Controller
  1088
- CAN Nodes 1 and 2 I/Os Sharing
  1089
  - Memory Map and Register Description
    1090
- Table 588. Detailed Mapping in CAN Subblocks
  1091
- Introduction
  1092
- Figure 540. Interprocessor Communication Diagram
  1093
- SIPI Block Diagram
  1094
- Standard Features
  1095
- Figure 542. SIPI Register Read Request
  1096
- Figure 545. SIPI Write Acknowledge
  1097
- Table 589. SIPI Header Command Coding
  1098
- Table 590. SIPI Header Channel Number Coding
  1099
- Transfer Types
  1100
- Read Transfer
  1101
- Figure 550. Read Answer Transfer (LFAST Frame Encapsulation Is Not Shown)
  1102
- Register Write Transfer
  1103
- Figure 553. Write Transfer (LFAST Frame Encapsulation Is Not Shown)
  1104
- Write Acknowledge Transfer
  1105
- ID Request Response
  1106
- Transfer API and Flow Charts
  1107
- Figure 559. SIPI Single Register Write API – Flow Chart
  1108
- Figure 560. SIPI Multiple Register Write API
  1109
- Figure 561. SIPI Single Register Read API
  1110
- Figure 562. SIPI Multiple Register Read API
  1111
- Figure 563. SIPI Data Stream Model
  1112
- Figure 565. SIPI Data Stream Model - Target
  1113
- DMA Programming Sequence
  1114
- Module Disable (MD)
  1115
- Acknowledge Error
  1116
- SIPI Control and Status Overview
  1117
- Memory Map and Register Description
  1118
  - Register Descriptions
    1120
- Table 595. Csrn Field Descriptions
  1122
- Table 596. Sipi_Cirn Field Descriptions
  1123
- Table 597. Sipi_Ctorn Field Descriptions
  1124
- Table 598. Sipi_Ccrcn Field Descriptions
  1125
- Table 600. Sipi_Cdrn Field Descriptions
  1126
- Table 602. SIPI_MCR Field Descriptions
  1127
- Table 603. SIPI_SR Field Descriptions
  1129
- Table 604. SIPI_MAXCR Field Descriptions
  1130
- Table 605. SIPI_ARR Field Descriptions
  1131
- Table 606. SIPI_ACR Field Descriptions
  1132
- Deserial Serial Peripheral Interface (DSPI)
  1134
  - Features
    1135
- DSPI Configurations
  1136
- Figure 583. DSPI with Queues and DMA
  1137
- Modes of Operation
  1138
- DSPI Signal Description
  1139
  - PCS[6] – PCS[7] — Peripheral Chip Selects 6 – 7
    1140
- DSPI Module Configuration Register (DSPI_MCR)
  1143
- DSPI Transfer Count Register (DSPI_TCR)
  1146
- Figure 586. DSPI Clock and Transfer Attributes Register (in Master Mode) (Dspi_Ctarn)
  1147
- Table 612. Dspi_Ctarn Field Descriptions
  1148
- Table 613. DSPI SCK Duty Cycle
  1150
- Table 614. Delay Scaler Encoding
  1151
- Figure 587. DSPI Clock and Transfer Attributes Register (in Slave Mode) (Dspi_Ctarn_Slave)
  1152
- DSPI Status Register (DSPI_SR)
  1153
- Table 617. DSPI_SR Field Descriptions
  1154
  - 46.3.6 DSPI Dma/Interrupt Request Select and Enable Register (DSPI_RSER
    1156
- Table 618. DSPI_RSER Field Descriptions
  1157
- DSPI PUSH FIFO Register in Master Mode (DSPI_PUSHR)
  1159
- Table 619. DSPI_PUSHR Field Descriptions
  1160
- DSPI PUSH FIFO Register in Slave Mode (DSPI_PUSHR_SLAVE)
  1161
- DSPI POP FIFO Register (DSPI_POPR)
  1162
- DSPI Transmit FIFO Registers (Dspi_Txfrn)
  1163
- DSPI DSI Configuration Register 0 (DSPI_DSICR0)
  1164
- Table 624. DSPI_DSICR0 Field Descriptions
  1165
- DSPI DSI Serialization Data Register 0 (DSPI_SDR0)
  1166
- DSPI DSI Alternate Serialization Data Register 0 (DSPI_ASDR0)
  1167
- DSPI DSI Transmit Comparison Register 0 (DSPI_COMPR0)
  1168
- DSPI DSI Configuration Register 1 (DSPI_DSICR1)
  1169
- DSPI DSI Serialization Source Select Register 0 (DSPI_SSR0)
  1170
- Table 630. DSPI_SSR0 Field Descriptions
  1171
- DSPI DSI Serialization Data Register 1 (DSPI_SDR1)
  1172
- DSPI DSI Alternate Serialization Data Register 1 (DSPI_ASDR1)
  1173
- DSPI DSI Transmit Comparison Register 1 (DSPI_COMPR1)
  1174
- DSPI DSI Serialization Source Select Register 1 (DSPI_SSR1)
  1175
- Table 638. DSPI_DIMR1 Field Descriptions
  1176
- DSPI Status Register Extended (DSPI_SREX)
  1177
  - Register Classification for Safety
    1178
- Functional Description
  1179
- Start and Stop of DSPI Transfers
  1180
- Serial Peripheral Interface (SPI) Configuration
  1181
- Deserial Serial Interface (DSI) Configuration
  1185
- Figure 614. DSI Serialization Diagram
  1187
- Combined Serial Interface (CSI) Configuration
  1188
- Figure 616. Example of System Using DSPI in CSI Configuration
  1189
- DSPI Baud Rate and Clock Delay Generation
  1190
- Table 645. after SCK Delay Computation Example
  1191
- Table 647. Peripheral Chip Select Strobe Assert Computation Example
  1192
- Transfer Formats
  1193
- Figure 619. DSPI Transfer Timing Diagram (MTFE = 0, CPHA = 0, FMSZ = 8)
  1194
- Figure 620. DSPI Transfer Timing Diagram (MTFE = 0, CPHA = 1, FMSZ = 8)
  1195
- Figure 627. Example of Non-Continuous Format (CPHA = 1, CONT = 0)
  1200
- Continuous Serial Communications Clock
  1202
- Figure 630. Continuous SCK Timing Diagram (CONT = 0)
  1203
- Slave Mode Operation Constraints
  1204
- Figure 632. DSPI Usage in the TSB Configuration
  1205
- Interleaved TSB (ITSB) Mode
  1207
- Table 649. Differences between TSB and ITSB Modes
  1208
- Figure 635. Sample MSC Downstream Transmission Using ITSB Mode
  1209
- Parity Generation and Check
  1210
  - Interrupts/Dma Requests
    1211
- Power Saving Features
  1214
  - Initialization/Application Information
    1215
- Initializing DSPI in Master/Slave Modes
  1216
- Delay Settings
  1217
- Calculation of FIFO Pointer Addresses
  1218
- Figure 636. TX FIFO Pointers and Counter
  1219
- Interprocessor Communications
  1221
- LFAST Operating Data Rates
  1222
- Figure 638. LFAST Frame Structure
  1223
- Table 653. Header Payload Sizes
  1224
  - Features
    1225
- Table 655. Register Conventions
  1227
  - Register Descriptions
    1228
- Table 657. SCR Field Descriptions
  1230
- Figure 643. Correlator Control Register (COCR)
  1231
- Table 658. COCR Field Descriptions
  1232
- Table 659. TMCR Field Descriptions
  1233
- Table 660. ALCR Field Descriptions
  1234
- Table 662. SLCR Field Descriptions
  1235
- Figure 648. ICLC Control Register (ICR)
  1236
- Table 663. ICR Field Descriptions
  1237
- Table 664. PICR Field Descriptions
  1238
- Table 666. TIER Field Descriptions
  1239
- Table 667. RIER Field Descriptions
  1240
- Table 668. RIIER Field Descriptions
  1241
- Table 669. LCR Field Description
  1243
- Table 670. UNSTCR Field Descriptions
  1245
- Table 671. Unstdrn Field Descriptions
  1246
- Table 673. PISR Field Descriptions
  1247
- Table 674. DFSR Field Descriptions
  1248
- Table 675. TISR Field Descriptions
  1249
- Table 676. RISR Field Descriptions
  1250
- Table 677. RIISR Field Descriptions
  1251
- Table 678. PLLLSR Field Descriptions
  1253
- Table 679. UNSRSR Field Descriptions
  1254
- Register Safety Classification Requirements
  1255
- Line Receiver (LR)
  1257
- Figure 666. Top Level Receive Controller
  1258
- Figure 667. Hunt Correlation Mode
  1259
- Table 681. High Speed 4 Phase Selection - Sampling Procedure
  1260
- Table 682. Low Speed 4 Phase Selection - Sampling Procedure
  1261
- Figure 670. Samplers, each Sampler Has 3 Registers
  1262
- Figure 671. Sampler 5 Logic
  1263
- Transmit Controller
  1265
- Table 684. Priority Levels for the Transmit Controller
  1266
- Figure 674. Example of Sleep Mode
  1268
- CTS Mode Support
  1269
- Frames Supported
  1270
- Table 687. Supported ICLC Payloads
  1273
- Test and Debug Support
  1276
- Figure 676. Rx Loopback Mode
  1277
- Figure 677. Rx LVDS Loopback Mode
  1278
- Figure 678. Tx Loopback Mode Without Automatic Frame Generation
  1279
- Figure 679. Automatic Loopback Test Status Signal Timings
  1280
- Figure 680. Tx Loopback Mode with Automatic Frame Generation
  1281
- Figure 681. Tx LVDS Loopback (External) Mode with Automatic Frame Generation
  1282
- Interrupts
  1283
- Table 690. Recommended Receive Exception Handling Mechanism
  1284
- Packet Memory
  1285
- Resets
  1286
- Slow Speed Clock
  1287
- Figure 683. External Clock Muxing of Lfast_Sysclk
  1288
- Figure 684. External Clock Muxing of Lfast_Sysclk of 20/26 Mhz
  1289
- Rx Controller Clocks
  1290
- Tx Controller Clocks
  1291
- Figure 688. Transmit Clocks Muxing
  1292
- Introduction
  1293
- Figure 689. FEC Block Diagram
  1294
- Table 695. FEC Sub-Block Descriptions
  1295
- Features
  1296
- Interface Options
  1297
- External Signal Description
  1298
- Memory Map and Register Definition
  1299
- Table 698. FEC Register Map
  1300
- Interrupt Event Register (EIR)
  1302
- Table 699. EIR Field Descriptions
  1303
- Interrupt Mask Register (EIMR)
  1304
- Receive Descriptor Active Register (RDAR)
  1305
- Transmit Descriptor Active Register (TDAR)
  1306
- Ethernet Control Register (ECR)
  1307
- Table 704. MMFR Field Descriptions
  1308
- MII Speed Control Register (MSCR)
  1309
- MIB Control Register (MIBC)
  1310
- Table 708. RCR Field Descriptions
  1311
- Transmit Control Register (TCR)
  1312
- Physical Address Lower Register (PALR)
  1313
- Physical Address Upper Register (PAUR)
  1314
- Descriptor Individual Upper Address Register (IAUR)
  1315
- Descriptor Group Lower Address Register (GALR)
  1316
- FIFO Receive Bound Register (FRBR)
  1317
- Receive Descriptor Ring Start Register (ERDSR)
  1318
- Receive Buffer Size Register (EMRBR)
  1319
- Count of Frames Not Counted Correctly (RMON_T_DROP)
  1320
- RMON Tx Multicast Packets (RMON_T_MC_PKT)
  1321
- RMON Tx Packets < 64 Bytes, Bad CRC (RMON_T_FRAG)
  1322
- RMON Tx Collision Count (RMON_T_COL)
  1323
- RMON Tx 128 to 255 Byte Packets (RMON_T_P128TO255)
  1324
- RMON Tx 1024 to 2047 Byte Packets (RMON_T_P1024TO2047)
  1325
- Count of Transmitted Frames Not Counted Correctly (IEEE_T_DROP)
  1326
- Frames Transmitted with Multiple Collisions (IEEE_T_MCOL)
  1327
- Frames Transmitted with Excessive Collisions (IEEE_T_EXCOL)
  1328
- Frames Transmitted with SQE Error (IEEE_T_SQE)
  1329
- Count of Received Frames Not Counted Correctly (RMON_R_DROP)
  1330
- RMON Rx Multicast Packets (RMON_R_MC_PKT)
  1331
- RMON Rx Packets < 64 Bytes, Bad CRC (RMON_R_FRAG)
  1332
- Reserved (RMON_R_RESVD_0)
  1333
- RMON Rx 128 to 255 Byte Packets (RMON_R_P128TO255)
  1334
- RMON Rx 1024 to 2047 Byte Packets (RMON_R_P1024TO2047)
  1335
- Count of Received Frames Not Counted Correctly (IEEE_R_DROP)
  1336
- Frames Received with Alignment Error (IEEE_R_ALIGN)
  1337
- Functional Description
  1338
- MII Management Frame Structure
  1339
- Buffer Descriptors
  1340
- Table 781. Receive Buffer Descriptor Field Descriptions
  1342
- Table 782. Transmit Buffer Descriptor Field Descriptions
  1344
- Initialization Sequence
  1345
- Microcontroller Initialization
  1346
- Table 784. MII Mode
  1347
- FEC Frame Transmission
  1348
- FEC Frame Reception
  1349
- Ethernet Address Recognition
  1350
- Figure 773. Ethernet Address Recognition—Receive Block Decisions
  1351
- Hash Algorithm
  1352
- Table 787. Destination Address to 6-Bit Hash
  1353
- Full Duplex Flow Control
  1355
- Inter-Packet Gap (IPG) Time
  1356
- RMII Echo
  1357
  - Introduction
    1359
  - Features
    1360
- Modes of Operation
  1361
- Block Diagram
  1362
- Design Overview
  1363
- External Signal Description
  1364
- Table 789. SENT Memory Map
  1365
  - Register Descriptions
    1366
- Table 790. GBL_CTRL Field Descriptions
  1367
- Table 791. CHNL_EN Field Descriptions
  1369
- Table 792. GBL_STATUS Field Descriptions
  1370
- Figure 781. Fast Message Ready Status Register (FMSG_RDY)
  1371
- Table 793. FMSG_RDY Field Descriptions
  1372
- Table 794. SMSG_RDY Field Descriptions
  1373
- Table 795. DATA_CTRL1 Field Descriptions
  1374
- Table 796. DATA_CTRL2 Field Descriptions
  1376
- Table 797. FDMA_CTRL Field Descriptions
  1378
- Table 798. SDMA_CTRL Field Descriptions
  1379
- Table 799. FRDY_IE Field Descriptions
  1380
- Table 800. SRDY_IE Field Descriptions
  1381
- Table 801. DMA_FMSG_DATA Field Descriptions
  1382
- Table 802. DMA_FMSG_CRC Field Descriptions
  1383
- Table 803. DMA_FMSG_TS Field Descriptions
  1384
- Table 804. DMA_SMSG_BIT3 Field Descriptions
  1385
- Figure 793. DMA Slow Serial Message Bit2 Read Register (DMA_SMSG_BIT2)
  1386
- Table 805. DMA_SMSG_BIT2 Field Descriptions
  1387
- Table 806. DMA_SMSG_TS Field Descriptions
  1388
- Table 807. Chn_Clk_Ctrl Field Descriptions
  1389
- Table 808. Chn_Status Field Descriptions
  1390
- Table 809. Chn_Config Field Descriptions
  1393
- Register Classification for Safety
  1396
  - Functional Description
    1397
- DMA Read Logic
  1398
- Figure 798. Fast Message DMA Read Logic
  1399
- Figure 799. Slow Serial Message DMA Read Logic
  1401
- Message Reading Via Interrupts
  1402
- Overflow Behavior
  1403
- Adjustment for Variation in Sensor (Tx) Clock
  1404
- Receiver Diagnostics
  1405
- Time Stamp Logic
  1407
- Bus Idle Diagnostic
  1408
- System Bus Clock Requirements
  1409
- High Frequency Receiver Clock (Protocol Clock) Requirements
  1410
- Introduction
  1411
- Figure 805. Block Diagram
  1412
- Main Features
  1413
  - UART Mode Features
    1414
- Figure 806. Frames
  1415
- Linflexd Features
  1416
- Figure 812. Operating Modes
  1417
- Figure 813. Linflexd Pins
  1418
- Figure 814. Incomplete Response (for Example, Missing Checksum)
  1422
- Figure 815. no Response
  1423
- Figure 816. Identifier List Mode
  1426
- Table 810. 10-Bit-Shift-Register Sample Register
  1427
- Figure 818. Start Detection and Sampling for over Sampling Rate = 4 (Case 1)
  1429
- Figure 820. Start Detection and Sampling for over Sampling Rate = 4 (Case 2B)
  1430
- Figure 823. Start Detection and Sampling for over Sampling Rate = 4 (Case 5)
  1431
- Timer
  1432
- UART Mode
  1433
- Figure 827. UART Mode 16-Bit Data Frame
  1434
- Table 811. BDRL Access in UART Mode
  1435
- Table 812. BDRM Access in UART Mode
  1436
- DMA Interface
  1438
- Table 814. Linflexd DMA Control Fields Description
  1440
- Table 824. TCD Setting – UART – Rx Mode
  1453
- Register Description
  1458
- Table 827. LINIER Field Descriptions
  1461
- Table 828. LINSR Field Descriptions
  1463
- Table 829. LINESR Field Descriptions
  1466
- Table 830. UARTCR Field Descriptions
  1468
- Table 831. UARTSR Field Descriptions
  1472
- Table 832. LINTCSR Field Descriptions
  1475
- Table 833. LINOCR Field Descriptions
  1476
- Table 834. LINTOCR Field Descriptions
  1477
- Table 835. LINFBRR Field Descriptions
  1478
- Table 836. LINIBRR Field Descriptions
  1479
- Table 837. LINCFR Field Descriptions
  1480
- Table 838. LINCR2 Field Descriptions
  1481
- Table 839. BIDR Field Descriptions
  1482
- Table 840. BDRL Field Descriptions
  1483
- Table 841. BDRM Field Descriptions
  1484
- Table 842. IFER Field Descriptions
  1485
- Table 844. IFMR Field Descriptions
  1486
- Table 845. Ifcr2N Field Descriptions
  1487
- Table 846. Ifcr2N+1 Field Descriptions
  1488
- Table 847. GCR Field Descriptions
  1489
- Figure 867. UART Preset Timeout Register (UARTPTO)
  1490
- Table 848. UARTPTO Field Descriptions
  1491
- Table 849. UARTCTO Field Descriptions
  1492
- Table 851. DMARXE Field Descriptions
  1493
- Register Map
  1494
- Programming Considerations
  1496
- Master Node
  1497
- Slave Node
  1498
- Extended Frames
  1503
- UART Mode
  1504
- Figure 898. Interrupt Diagram
  1506
  - Reset Generation Module (MC_RGM)
    1507
- Figure 899. MC_RGM Block Diagram
  1508
- Features
  1509
  - External Signal Description
    1510
- Memory Map and Register Definition
  1511
- Register Descriptions
  1512
- Table 856. 'Destructive' Event Reset Disable (RGM_DERD) Register Field Descriptions
  1514
- Table 857. 'Destructive' Event Alternate Request (RGM_DEAR) Register Field Descriptions
  1515
- Table 858. Destructive' Bidirectional Reset Enable (RGM_DBRE) Register Field Descriptions
  1516
- Figure 904. 'Functional' Event Status (RGM_FES) Register
  1517
- Table 859. 'Functional' Event Status (RGM_FES) Register Field Descriptions
  1518
- Table 860. 'Functional' Event Reset Disable (RGM_FERD) Register Field Descriptions
  1520
- Field Descriptions
  1522
- Field Descriptions
  1524
- Table 863. 'Functional' Event Short Sequence (RGM_FESS) Register Field Descriptions
  1526
- Table 864. 'Functional' Reset Escalation Threshold (RGM_FRET) Register Field Descriptions
  1528
- Table 865. External Reset Output Extension Control (RGM_EROEC) Register Field Descriptions
  1529
- Table 866. Peripheral Reset Registers (RGM_PRST0) Field Descriptions
  1530
- Table 867. Peripheral Reset Registers (RGM_PRST1) Field Descriptions
  1531
- Table 868. Peripheral Reset Registers (RGM_PRST2) Field Descriptions
  1532
- Table 869. Peripheral Reset Registers (RGM_PRST3) Field Descriptions
  1534
- Figure 915. Peripheral Reset Register 4 (RGM_PRST4)
  1535
- Functional Description
  1536
- Figure 916. MC_RGM State Machine
  1537
- Destructive' Resets
  1539
- Functional' Resets
  1540
- Alternate Event Generation
  1541
- Individual Peripheral Resets
  1542
  - Boot Assist Flash (BAF)
    1543
  - Functional Description
    1544
- Flow of Control
  1545
- Table 876. BAF DCF Client List
  1547
- Figure 918. SEC_SWT_CPU Bit Configuration
  1548
- Table 877. SEC_SWT_CPU Field Description
  1549
- Figure 920. DATA32 DCF Client Configuration
  1550
- Optionally Perform a Serial Boot
  1551
- Figure 923. Flow of Control During Serial Boot
  1552
- Figure 924. Start Address, VLE Bit, NO_ECHO Bit and Download Size in Bytes
  1555
- Serial Boot Configuration
  1556
- Table 880. M_CAN_1 Baud Rates
  1557
- Table 882. M_CAN Serial Boot Mode Download Protocol
  1558
- Resources
  1559
- System Status and Configuration Module (SSCM)
  1560
  - Features
    1561
  - Register Descriptions
    1562
- Table 886. MEMCONFIG Field Descriptions
  1563
- Table 887. ERROR Field Descriptions
  1564
  - Functional Description
    1565
- Table 890. DCF Start Record
  1566
- ECC Error Monitoring
  1567
- BAF Configuration
  1568
- Initialization and Application Information
  1569
- Power Management Controller Digital Interface (Pmc_Dig)
  1570
- Figure 935. Digital PMC Block Diagram
  1571
  - Memory Map and Register Definition
    1572
  - Register Descriptions
    1573
- Table 899. GR_P Field Descriptions
  1575
- Table 900. IE_P Field Descriptions
  1576
- Table 901. EPR_VD2 Field Descriptions
  1578
- Table 902. EPR_VD3 Field Descriptions
  1579
- Table 904. RES_VD3 Field Descriptions
  1580
- Table 905. EPR_VD10 Field Descriptions
  1581
- Table 906. REE_VD10 Field Descriptions
  1582
- Table 907. RES_VD10 Field Descriptions
  1583
- Table 908. EPR_VD14 Field Descriptions
  1584
- Table 909. REE_VD14 Field Descriptions
  1585
- Table 910. RES_VD14 Field Descriptions
  1586
- Table 912. MREG_CTRL Field Descriptions
  1587
- Table 913. EPR_TD Field Descriptions
  1588
- Table 914. REE_TD Field Descriptions
  1589
- Figure 954. Temperature Sensor Configuration Register (CTL_TD)
  1590
- Analog PMC Interface
  1591
- Temperature Sensor Interface Logic
  1592
- Power Control Unit (MC_PCU)
  1594
  - External Signal Description
    1595
- Table 918. Power Domain Status Register (PCU_PSTAT) Field Descriptions
  1596
- Mode Entry Module (MC_ME)
  1597
- Figure 957. MC_ME Block Diagram
  1598
  - Features
    1599
  - External Signal Description
    1600
- Memory Map
  1601
  - Register Description
    1604
- Table 921. Global Status Register (ME_GS) Field Descriptions
  1605
- Figure 959. Mode Control Register (ME_MCTL)
  1606
- Table 922. Mode Control Register (ME_MCTL) Field Descriptions
  1607
- Table 923. Mode Enable Register (ME_ME) Field Descriptions
  1608
- Table 924. Interrupt Status Register (ME_IS) Field Descriptions
  1609
- Table 925. Interrupt Mask Register (ME_IM) Field Descriptions
  1610
- Table 926. Invalid Mode Transition Status Register (ME_IMTS) Field Descriptions
  1611
- Figure 964. Debug Mode Transition Status Register (ME_DMTS)
  1612
- Table 927. Debug Mode Transition Status Register (ME_DMTS) Field Descriptions
  1613
- Figure 965. RESET Mode Configuration Register (ME_RESET_MC)
  1616
- Figure 967. SAFE Mode Configuration Register (ME_SAFE_MC)
  1617
- Figure 969. RUN0...3 Mode Configuration Registers (ME_RUN0...3_MC)
  1618
- Table 928. Mode Configuration Registers (Me_<Mode>_Mc) Field Descriptions
  1619
- Figure 972. Peripheral Status Register 0 (ME_PS0)
  1621
- Figure 974. Peripheral Status Register 2 (ME_PS2)
  1622
- Table 929. Peripheral Status Registers (Me_Psn) Field Descriptions
  1623
- Table 930. Run Peripheral Configuration Registers (ME_RUN_PC0...7) Field Descriptions
  1624
- Table 931. Low-Power Peripheral Configuration Registers (ME_LP_PC0...7) Field Descriptions
  1625
- Figure 980. Core Status Register (ME_CS)
  1626
- Table 933. Core Status Register (ME_CS) Field Descriptions
  1627
- Figure 982. Core Control Registers (ME_CADDR0)
  1628
  - Functional Description
    1629
- Modes Details
  1630
- Mode Transition Process
  1633
- Table 936. MC_ME Resource Control Overview
  1634
- Table 937. MC_ME System Clock Selection Overview
  1638
- Figure 984. MC_ME Transition Diagram
  1640
- Protection of Mode Configuration Registers
  1641
- Peripheral Clock Gating
  1643
- Figure 985. MC_ME Application Example Flow Diagram
  1644
- Overview
  1645
- Additional Debug Facilities
  1646
- Sharing Debug Resources by Software/Hardware
  1647
- Software Debug Events and Exceptions
  1648
- Instruction Address Compare Event
  1649
- Data Address Compare Event
  1650
- Table 938. DAC Events and Resultant Updates
  1651
- Trap Debug Event
  1653
- Interrupt Taken Debug Event
  1654
- Critical Return Debug Event
  1655
- Debug Address and Value Registers
  1656
- Debug Control and Status Registers
  1657
- Table 939. DBCR0 Field Descriptions
  1658
- Table 940. DBCR1 Field Descriptions
  1660
- Table 941. DBCR2 Field Descriptions
  1662
- Figure 991. DBCR4 Register
  1665
- Table 942. DBCR4 Field Descriptions
  1666
- Table 943. DBCR5 Field Descriptions
  1668
- Figure 993. DBCR6 Register
  1669
- Table 944. DBCR6 Field Descriptions
  1670
- Table 945. DBCR7 Field Descriptions
  1671
- Table 946. DBCR8 Field Descriptions
  1673
- Table 947. DBSR Field Descriptions
  1675
- External Debug Resource Allocation Control (EDBRAC0) Register
  1676
- Figure 998. External Debug Resource Allocation Control (EDBRAC0) Register
  1677
- Table 948. EDBRAC0 Field Descriptions
  1678
- Table 949. EDBRAC0 Resource Control
  1680
- Debug Event Select Register (DEVENT) Register
  1685
- Using Debug Resources for Stack Limit Checking
  1686
- External Debug Support
  1688
- External Debug Registers
  1689
- Table 952. EDBCR0 Field Descriptions
  1690
- Table 953. EDBSR0 Field Descriptions
  1691
- Table 954. EDBSRMSK0 Field Descriptions
  1692
- Once Introduction
  1694
- Figure 1005.Once TAP Controller and Registers
  1695
- Figure 1006.Once Controller Implementation
  1696
- Jtag/Once Pins
  1697
- Once Interface Signals
  1698
- Once Controller and Serial Interface
  1700
- Table 956. Once Status Register Field Descriptions
  1701
- Table 957. OCMD Field Descriptions
  1702
- Table 958. Once Register Addressing
  1703
- Figure 1010.Once Control Register (OCR)
  1705
- Access to Debug Resources
  1706
- Table 960. Once Register Access Requirements
  1707
- Methods of Entering Debug Mode
  1708
- CPU Status and Control Scan Chain Register (CPUSCR)
  1709
- Figure 1011.CPU Scan Chain Register (CPUSCR)
  1710
- Table 961. CTL Field Descriptions
  1711
- Reserved Registers (Reserved)
  1715
- Table 962. Watchpoint Output Signal Assignments
  1716
- Basic Steps for Enabling, Using, and Exiting External Debug Mode
  1718
  - Introduction
    1720
- Figure 1013.DCI Block Diagram
  1721
- Operating Modes
  1722
- Table 964. DCI Operating Modes
  1723
- Table 965. Nexus Reset Truth Table
  1724
- Figure 1015.DCI Debug Control Mechanism
  1725
- Figure 1016.DCI Debug Signal Generation
  1726
- Figure 1017.DCI EVTO Management
  1727
  - External Signal Description
    1728
- Table 966. DCI_CR Field Descriptions
  1729
- DCI Evtx Pin Multiplexing Control Register (DCI_PINCR)
  1730
  - Introduction
    1731
  - Features
    1732
  - External Signal Description
    1733
  - Register Description
    1734
- JTAG_PASSWORD Register
  1735
  - Boundary Scan Register
    1736
- Figure 1025.IEEE 1149.1-2001 TAP Controller Finite State Machine
  1737
- JTAGC Block Instructions
  1738
- Boundary Scan
  1741
- References
  1743
  - Introduction
    1744
- Types of Operation
  1745
- TAP.7 Architecture
  1746
- Protocols
  1747
- Table 973. Class/Protocol Relationship
  1748
- Operating Models
  1749
- T4 Functions
  1750
- Figure 1029.Conceptual View of the EPU Reset Logic and State Machines
  1751
- Table 974. Reset State Descriptions
  1753
- Start-Up Options
  1754
- Figure 1031.Conceptual View of Technology Selection Mechanism
  1755
- TAPC State Machine
  1756
- EPU (Extended Protocol Unit) Operation
  1757
- EPU Registers
  1759
- Table 978. TAP.7 Controller Register List (Managed with Commands)
  1760
- Table 979. Scan Format Register Values
  1762
- Table 980. RDBACK Register Format
  1765
- Table 981. Configuration Register 0 Format
  1766
- EPU Commands
  1769
- Figure 1033.Dr_Scan Sequence Used for Command Creation
  1770
- Table 983. TAP.7 Controller Command List
  1771
- Table 984. Store Miscellaneous Control
  1773
- Table 985. Store Conditional 1 Bit (STC1)
  1774
- Table 988. Make Conditional Group Member (MCM)
  1775
- Table 990. Scan Bit (SCNB)
  1776
- EPU Operating States
  1777
- System and EPU Paths
  1778
- Figure 1035.Conceptual Block Diagram of the APU Functions
  1780
- Operation
  1781
- Escape Sequences
  1782
- Figure 1037.Scan Packet Sequence
  1783
- Figure 1038.Serialization and De-Serialization of Scan Packet Information
  1784
- Figure 1039.CPA State Entry from BPA State with Continued Online Operation
  1785
- Figure 1040.CPA State Entry from the SPA State with Continued Online Operation
  1786
- Figure 1041.CPA State Entry from the BPA State with Offline Operation
  1787
- Figure 1042.CPA State Entry from the SPA State with Offline Operation
  1788
- Configuration Change Packets (CP)
  1789
- Table 993. Factors Determining the SP Payload Content
  1790
- Table 994. Mscan Scan Format Use Case Summary
  1792
- Figure 1044.Oscan Scan Packet Content/Tapc State Relationships
  1793
- Table 996. Oscan Scan Format Use Case Summary
  1794
  - Functional Description
    1795
  - Introduction
    1796
- Register Definition
  1797
- Table 1000. JDC_MSR Register Field Descriptions
  1798
- Table 1001. JDC_JOUT_IPS Register Field Descriptions
  1799
- Non-Memory Mapped Register Definition
  1800
  - Functional Description
    1801
  - Introduction
    1803
- Feature Description
  1804
- JTAGM Ready Signal
  1805
- JTAGM Configuration and Status Monitoring
  1806
- Software Interface
  1807
- Table 1007. JTAGM_MCR Register Field Descriptions
  1808
- Table 1008. JTAGM_SR Register Field Descriptions
  1810
- Figure 1056.JTAGM_DOR0 Register
  1811
- Table 1009. JTAGM_DOR0 Register Field Descriptions
  1812
- Table 1012. JTAGM_DOR3 Register Field Descriptions
  1813
- Table 1014. JTAGM_DIR1 Register Field Descriptions
  1814
- Sequence Processing Unit (SPU)
  1815
- Overview
  1816
  - Features
    1818
- SPU Actions
  1819
- Operation Mode
  1820
- Table 1015. SPU Register Summary
  1821
  - Register Descriptions
    1825
- Figure 1065.L1SEL1 Register Format
  1826
- Figure 1068.L1SEL4 Register Format
  1827
- Table 1016. ITLD Register Field Descriptions
  1828
- Table 1017. C2PEVP Register Field Descriptions
  1829
- Table 1018. C2PIS Register Field Descriptions
  1830
- Figure 1076.Level2 Mux and Gates Input Pin Routing for State0
  1831
- Table 1019. L2Nsel0 Register Field Descriptions
  1832
- Table 1020. L2Nsel1 Register Field Descriptions
  1833
- Table 1021. L2Nsel2 Register Field Descriptions
  1834
- Figure 1080.L2Nsel3 Register Format
  1835
- Table 1022. L2Nsel3 Register Field Descriptions
  1836
- Table 1023. Ioicn Register Field Descriptions
  1837
- Table 1024. SCTRL Register Field Descriptions
  1838
- Table 1025. Sngc Register Field Descriptions
  1841
- Table 1026. SS Register Field Descriptions
  1842
- Table 1027. SE Register Field Descriptions
  1844
- Table 1028. SPU Action Decoder
  1845
- Figure 1086.Snta0 Register Format
  1846
- Table 1029. Snta0 Register Field Descriptions
  1847
- Table 1031. Snfa0 Register Field Descriptions
  1848
- Table 1032. Snfa1 Register Field Descriptions
  1849
- Table 1033. Trace Group Configuration Register Field Descriptions
  1850
- Table 1034. INTS Register Field Descriptions
  1851
- Table 1036. Ccmpn Register Field Descriptions
  1852
- Table 1037. CCOMS Register Field Descriptions
  1853
  - Functional Description
    1854
- Processor Exception Vector Encoding
  1856
- State Logic Unit (SLU)
  1857
- Sequence Formation
  1858
- Figure 1099.Example of a Simple Configurable If-Then-Else Sequence
  1859
- Figure 1100.Complex Sequence Example
  1860
- Performance Counters/Timers Unit
  1861
- Action Unit
  1862
  - Format for CKSRC & CKDATA Values
    1863
- Development Trigger Semaphore (DTS)
  1864
- Figure 1103.DTS Block Diagram
  1865
- DTS Device Connections
  1866
- DTS Register Access
  1867
  - Register Descriptions
    1868
- Table 1046. DTS_STARTUP Register Field Descriptions
  1869
- Example Application
  1870
- Figure 1110.DTS Startup Sequence Example
  1872
  - Introduction
    1873
- Overview
  1874
  - Register Descriptions
    1875
- Table 1050. NAR_CR Field Descriptions
  1876
- Figure 1113.NAR Status Register (NAR_ST)
  1877
- Message Filtering Registers
  1878
- Table 1052. NAR_SFR Field Descriptions
  1879
- Table 1053. NAR_TFR Field Descriptions
  1880
- Trace Memory Bus Configuration Registers
  1881
- Table 1054. NAR_TBAHI Field Descriptions
  1882
- Suppress Mode Triggers Register (NAR_STCR)
  1883
- Table 1057. NAR_STCR Field Descriptions
  1884
- Receive Queue Client Disable Register (NAR_CDR)
  1885
- Table 1059. NAR_CDR Field Descriptions
  1886
  - Functional Description
    1887
- Operation Modes
  1888
- Table 1062. NAR Transmit Operations
  1889
- Data Reception and Arbitration
  1890
- Suppress Mode
  1891
- Stall Detection
  1892
- Output Arbitration
  1893
- Message Translation and Formatting
  1894
- Aurora Interface
  1895
- Internal Message Generation
  1896
- Table 1063. NAR Message Formats
  1897
- Table 1064. NAR Error Types
  1898
- Table 1065. Configuration Error Codes
  1899
- Timestamp Function
  1900
- Overlay and Internal Trace Memory Full Status Generation
  1901
- Configuration/Debug Interface JTAG (1149.1)
  1902
- Table 1067. Implemented Instructions
  1903
- Table 1068. Loading NEXUS-ENABLE Instruction
  1904
- Trace Memory Bus Controller
  1905
- Legacy Client Interface Controller
  1907
- Initialization Information
  1908
  - Introduction
    1909
  - Feature List
    1910
- Functional Block Diagram
  1912
- Interaction with Low Power Modes
  1913
- Table 1071. Supported Tcodes
  1914
- Table 1072. Error Code (ECODE) Encoding (TCODE = 8)
  1917
- Table 1073. Error Type (ETYPE) Encoding (TCODE = 8)
  1918
- Nexus 3 Programmer's Model
  1919
- Client Select Control (CSC) Register
  1920
  - Port Configuration Register (PCR) — Reference Only
    1921
- Nexus Development Control Register 1 (DC1)
  1922
  - Nexus Development Control Registers 2 & 3 (DC2, DC3)
    1923
- Table 1081. DC2 Field Descriptions
  1924
- Figure 1134.Development Control 3 (DC3) Register
  1925
- Table 1082. DC3 Field Descriptions
  1926
- Nexus Development Control Register 4 (DC4)
  1927
- Development Status Register (DS)
  1928
- Table 1084. DS Field Descriptions
  1929
- Table 1085. WT Field Descriptions
  1930
- Table 1086. PTSTC Field Descriptions
  1931
- Table 1087. PTETC Field Descriptions
  1932
- Table 1088. DTSTC Field Descriptions
  1933
- Nexus Watchpoint Mask (WMSK) Register
  1934
- Nexus Overrun Control (OVCR) Register
  1935
- Data Trace Control (DTC) Register
  1936
- Table 1091. DTC Field Descriptions
  1937
- Data Trace Start Address Registers (DTSA1–4)
  1938
- Table 1092. Data Trace — Address Range Options
  1939
- Read/Write Access Control/Status (RWCS) Register
  1940
- Read/Write Access Data (RWD) Register
  1941
- Table 1096. RWD Byte Lane Mapping
  1942
- Read/Write Access Address (RWA)
  1943
- Nexus 3 Register Access Via Software
  1944
- Full Address Field (F-ADDR)
  1945
- Message Queue Overrun
  1946
- Table 1098. Message Type Priority and Message Dropped Responses
  1947
- Data Acquisition Message Priority Loss Response
  1948
- Error Messages
  1949
- Program Trace
  1950
- Branch Trace Messaging Types
  1951
- BTM Message for Mats
  1952
- Program Trace Message Fields
  1953
- Resource Full Messages
  1954
- Program Correlation Messages
  1955
- Program Trace Overflow Error Messages
  1956
- Table 1103. Program Trace Exception Summary
  1957
- Program Trace Direct/Indirect Branch with Sync Messages
  1958
- Enabling Program Trace
  1959
- Data Trace
  1960
- Data Trace Messaging (DTM)
  1961
- Table 1105. Data Trace Exception Summary
  1962
- DTM Operation
  1963
- Data Trace Timing Diagrams (8 MDO / 2 MSEO Configuration)
  1965
- Data Acquisition Trace Event
  1966
- Watchpoint Timing Diagram (2 MDO / 1 MSEO Configuration)
  1967
- External Hardware Trigger Controls
  1968
- Nexus 3 Read/Write Access to Memory-Mapped Resources
  1969
- Block Write Access
  1970
- Single Read Access
  1971
- Error Handling
  1972
- Nexus 3 Pin Interface
  1973
- Table 1110. Nexus 3 Auxiliary Pins
  1974
- Pin Protocol
  1975
- Figure 1184.Single Pin MSEO Transfers
  1976
- Rules for Output Messages
  1977
- Auxiliary Port Arbitration
  1978
- Table 1114. Indirect Branch Message Example (2 MDO / 1 MSEO)
  1979
- Table 1116. Direct Branch Message Example (2 MDO / 1 MSEO)
  1980
- Electrical Characteristics
  1981
- JTAG Sequence for Read Access of Memory-Mapped Resources
  1982
  - Register Protection (REG_PROT)
    1983
  - Modes of Operation
    1984
  - Memory Map
    1985
  - Register Descriptions
    1986
- Table 1124. Soft Lock Bits Vs. Protected Address
  1987
- Figure 1190.Global Configuration Register (GCR)
  1988
  - Functional Description
    1989
- Figure 1191.Change Lock Settings Directly Via Area #4
  1990
- Figure 1193.Change Lock Settings for 32-Bit Protected Addresses
  1991
- Access Errors
  1992
- Initialization/Application Information
  1993
- Password and Device Security Module (PASS)
  1994
- Memory Map and Register Definition
  1995
  - Register Descriptions
    1996
- Table 1128. LCSTAT Register Field Descriptions
  1997
- Table 1129. CHSEL Register Field Descriptions
  1998
- Table 1131. CIN Register Field Descriptions
  1999
- Table 1132. Lock0_Pgn Register Field Descriptions
  2000
- Table 1133. Lock1_Pgn Register Field Descriptions
  2001
- Figure 1204.Lock2_Pgn Register
  2002
- Table 1134. Lock2_Pgn Register Field Descriptions
  2003
- Table 1135. Lock3_Pgn Register Field Descriptions
  2004
- DCF Clients
  2006
  - Functional Description
    2007
- Flash Memory Read Protection
  2008
  - Initialization/Application Information
    2009
- Censoring and Uncensoring the Device
  2010
  - Introduction
    2012
  - Features
    2013
  - Register Descriptions
    2014
- Table 1143. NSR Field Descriptions
  2015
- Table 1144. NCR Field Descriptions
  2016
- Table 1145. WISR Field Descriptions
  2017
- Table 1146. IRER Field Descriptions
  2018
  - Functional Description
    2019
- External Wakeups/Interrupts
  2020
- Reset Management
  2021
- Glitch Filter and Pad Configuration
  2022
- Table 1149. Acronyms and Abbreviations
  2024
  - Revision History
    2028

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