Figure 1076.Level2 Mux And Gates Input Pin Routing For State0 - STMicroelectronics SPC572L series Reference Manual

RM0400
Mux 1
Mux 5
Mux 9
Mux 13
Mux 16
Note: If any SLU AND gate is unused, then its output is logic low (1'b0). Thus, if all four inputs of a
particular AND gate are at the default value 1'b1 (none of the inputs have been routed from
the Level 2 mux to the inputs of AND gates), then the output of that AND gate is logic low.
This provides protection to avoid the masking of other inputs to the OR gate.
63.5.1.2.1 Level2 Mux state n selection 0 (L2nSEL0)
Figure 1077
0x17 (State0)
0x1B (State1)
0x1F (State2)
0x23 (State3)
Offset
0x27 (State4)
0x2B (State5)
0x2F (State6)
0x33 (State7)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0 0
FirstANDInput4
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 1076. Level2 Mux AND gates input pin routing for State0
InAND1
1
2
3
4
InAND2
5
6
7
8
InAND3
9
10
11
12
InAND4
13
14
15
16
shows the format of the L2nSEL0 register where the state number, n = 0–7.
0 0
FirstANDInput3
Figure 1077. L2nSEL0 register format
DocID027809 Rev 4
OutAND1
1
OutAND2
2
OutAND3
3
OutAND4
4
If AND Gate is unused, the output is logic low
0 0
FirstANDInput2
Sequence Processing Unit (SPU)
Access: User read/write
8 7 6 5 4
0 0
FirstANDInput1
Event S0
OutOR
3 2 1 0
1831/2058
1863