Table 435. Stm_Cr Field Descriptions - STMicroelectronics SPC572L series Reference Manual

System Timer Module (STM)
Field
Counter Prescaler. Selects the clock divide value for the prescaler (1 - 256).
0x00 Divide system clock by 1
16:23
0x01 Divide system clock by 2
CPS
...
0xFF Divide system clock by 256
Freeze. Allows the timer counter to be stopped when the device enters debug mode.
30
0 STM counter continues to run in debug mode.
FRZ
1 STM counter is stopped in debug mode.
Timer Counter Enabled.
31
0 Counter is disabled.
TEN
1 Counter is enabled.
39.3.2.2 STM Count Register (STM_CNT)
The STM Count Register (STM_CNT) holds the timer count value.
Offset: 0x004
0 1 2 3 4
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
0:31
Timer count value used as the time base for all channels. When enabled, the counter increments at the
rate of the system clock divided by the prescale value.
CNT
39.3.2.3 STM Channel Control Register (STM_CCRn)
The STM Channel Control Register (STM_CCRn) has the enable bit for channel n of the
timer.
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Table 435. STM_CR field descriptions

5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Figure 380. STM Count Register (STM_CNT)
Table 436. STM_CNT field descriptions
DocID027809 Rev 4
Description
CNT
Description
RM0400
Access: Read/Write