System Timer Module (Stm) Configuration; Software Watchdog Timer (Swt) Configuration - STMicroelectronics SPC572L series Reference Manual

Device configuration
The GTM101 is an implementation of the Robert Bosch GmbH GTM timer subsystem. It is
not a single module, but a complex timer subsystem that consists of many modules that can
be used to implement highly complex timer functions.
6.6

System Timer Module (STM) configuration

The System Timer Module (STM) is a 32-bit timer designed to support commonly required
system and application software timing functions. The STM includes a 32-bit up counter and
four 32-bit compare channels with a separate interrupt source for each channel. The counter
is driven by the appropriate system clock divided by an 8-bit prescale value (1 to 256).
SPC572Lx includes one STM (STM_2)—which runs on the PBRIDGE_A clock domain—
with four 32-bit compare channels and fourteen 32-bit registers.
6.6.1

Software Watchdog Timer (SWT) configuration

SPC572Lx includes four SWTs.
Instance
SWT0
SWT1
SWT2
SWT3
The SWT has the following features:
•
32-bit time-out register to set the time-out period
•
Internal oscillator clock (16MIRC) is the clock source for timer operation.
•
Programmable selection of window mode or regular servicing
•
Programmable selection of reset or interrupt on an initial time-out
• Programmable selection of the servicing mode
•
Master access protection
• Hard and soft configuration lock bits
6.6.1.1 Reset assertion
The SWT can assert a reset when the watchdog timer expires. This reset causes a system
reset equivalent to assertion of the RESET pin.
6.6.1.2 Default configuration
On SPC572Lx, the SWTs come out of reset with the default reset values summarized in
Table 37. Minimum timeout value is 256 cycles for SWT0, SWT2 and SWT3.
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Table 36. Software Watchdog Timer (SWT) instances
Intended for Main Core_0 in the high-speed computational clock domain.
Intended for Main Core_1 in the high-speed computational clock domain.
Intended for Peripheral Core_2 in the peripheral clock domain. Elapsed times recorded in
timeout register are different from SWT0 and SWT1.
Intended for Checker Core_0s in the high-speed computational clock domain, within the
Safety Lake.
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Description
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