Critical Return Debug Event - STMicroelectronics SPC572L series Reference Manual

RM0400
57.2.10

Critical Return Debug Event

A Critical Return debug event (CRET) occurs if Critical Return debug events are enabled
(DBCR0
CRET
occur and be recorded in DBSR regardless of the setting of MSR
debug event occurs, the DBSR
If MSR
DE
the se_rfci), then DBSR
If MSR
DE
there exists no higher priority exception that is enabled to cause an interrupt. Debug
Save/Restore Register 0 will be set to the address of the se_rfci instruction.
57.2.11 External debug event
An External debug event (DEVT1, DEVT2) occurs if External debug events are enabled
(DBCR0
DEVT1
transitions to the asserted state while the CPU is not in the Stopped state. This event can
occur and be recorded in DBSR regardless of the setting of MSR
debug event occurs, DBSR
event is an asynchronous event, but is only sampled when the CPU m_clk is active.
57.2.12 Unconditional debug event
An Unconditional debug event (UDE) occurs when the Unconditional Debug Event (p_ude)
input transitions to the asserted state. The Unconditional debug event is the only debug
event that does not have a corresponding enable bit for the event in DBCR0. This event can
occur and be recorded in DBSR regardless of the setting of MSR
debug event occurs, the DBSR
event is an asynchronous event.
57.2.13 Performance Monitor Interrupt debug event
A Performance Monitor Interrupt debug event (PMI) occurs if Performance Monitor Interrupt
debug events are enabled (PMGC0
occurs. This event can occur and be recorded in DBSR regardless of the setting of MSR
When a Performance Monitor Interrupt debug event occurs, DBSR
the debug exception. This debug event is an asynchronous event.
57.3 Debug registers
This section describes debug-related registers that are software accessible. These registers
are intended for use by special debug tools and debug software, not by general application
code.
Access to these registers (other than DBSR) by software is conditioned by the External
Debug mode control bit (EDBCR0
EDBRAC0, which can be set by the hardware debug port. If EDBCR0
in EDBRAC0 corresponding to the resource is cleared, software is prevented from
modifying debug register values other than in DBSR, since the resource is not "owned" by
software. Software always has ownership of DBSR. Execution of a
targeting a debug register or register field not "owned" by software will not cause
=1) and an attempt is made to execute an se_rfci instruction. This event can
=0 at the time of the execution of the se_rfci (i.e. before the MSR is updated by
is also set to 1 to record the imprecise debug event.
IDE
=1 at the time of the execution of the se_rfci, a Debug interrupt will occur provided
=1 or DBCR0
DEVT2
DEVT{1,2}
UDE
DocID027809 Rev 4
bit is set to 1 to record the debug exception.
CRET
=1), and the respective p_devt1 or p_devt2 input signal
is set to '1' to record the debug exception. This debug
bit is set to '1' to record the debug exception. This debug
=1), and a performance monitor interrupt event
UDI
) and the settings of debug control register
EDM
e200z215An3 Core Debug Support
. When a Critical Return
DE
. When an External
DE
. When an Unconditional
DE
is set to '1' to record
PMI
is set and if the bit
EDM
mtspr
instruction
.
DE
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