Memory Map And Register Descriptions - STMicroelectronics SPC572L series Reference Manual

Sigma-Delta Analog-to-Digital Converter (SDADC) Digital Interface
Signal I/O
Clock input provided by external modulator.
State meaning
EMCLK I
35.6

Memory map and register descriptions

35.6.1 Memory map
This section provides the memory map for the SDADC block.
Offset or
address
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020
1. Saf-Relv = Safety Relevant, No-Saf = Not Safety Relevant.
35.6.2 Register descriptions
This section provides the block's register bit descriptions in address order.
35.6.2.1 Module Configuration Register (MCR)
The Module Configuration register (MCR) consists of different control bits to select the
operating modes and various configuration settings which define the behavior of the
SDADC block.
736/2058
Table 356. Detailed signal descriptions(Continued)
Asserted—clock high level
Negated—clock low level
Assertion—May occur at any time, but clock is valid only when external modulator
Timing is selected by MCR[MODSEL] = 1.
Negation—Ignored when external modulator is not selected.
Table 357. SDADC Digital interface memory map
Module Configuration Register (MCR)
Channel Selection Register (CSR)
Reset Key Register (RKR)
Status Flag Register (SFR)
Request Select and Enable Register (RSER)
Output Settling Delay Register (OSDR)
FIFO Control Register (FCR)
Software Trigger Key Register (STKR)
Converted Data Register (CDR)
DocID027809 Rev 4
Description
Register
RM0400
Register
classification Location
(1)
Saf-Relv on page 736
Saf-Relv on page 739
No-Saf on page 741
No-Saf on page 742
Saf-Relv on page 744
Saf-Relv on page 745
Saf-Relv on page 746
No-Saf on page 747
No-Saf on page 748