Access To Debug Resources - STMicroelectronics SPC572L series Reference Manual

e200z215An3 Core Debug Support
Table 959
Bit Name
0:28 — Reserved
Wakeup Request Bit
This control bit may be used to force the p_wakeup output signal to be asserted. This control
function may be used by debug firmware to request that the chip-level clock controller restore
29 WKUP
the m_clk input to normal operation regardless of whether the CPU is in a low power state to
ensure that debug resources may be properly accessed by external hardware through scan
sequences.
Force Breakpoint Debug Mode Bit
This control bit is used to determine whether the processor is operating in breakpoint debug
enable mode or not. The processor may be placed in breakpoint debug enable mode by
setting this bit. In breakpoint debug enable mode, execution of the 'bkpt' pseudo-instruction
30 FDB
will cause the processor to enter debug mode, as if the jd_de_b input had been asserted.
This bit is qualified with EDBCR0
Note: This bit has no effect on e_dnh or se_dnh instruction operation.
CPU Debug Request Control Bit
This control bit is used to unconditionally request the CPU to enter Debug mode. The CPU
will indicate that Debug mode has been entered via the data scanned out in the shift-IR state.
31 DR
0 No Debug mode request
1 Unconditional Debug mode request
When the DR bit is set, the processor will enter Debug mode at the next instruction boundary.
57.5.7

Access to debug resources

Resources contained in the OnCE Module that do not require the processor core to be
halted for access may be accessed while the e200z215An3 core is running, and will not
interfere with processor execution. Accesses to other resources such as the CPUSCR
require the e200z215An3 core to be placed in debug mode to avoid synchronization
hazards. Debug firmware may ensure that it is safe to access these resources by
determining the state of the e200z215An3 core prior to access. Note that a scan operation
to update the CPUSCR is required prior to exiting debug mode if debug mode has been
entered.
Some cases of write accesses other than accesses to the OnCE Command and Control
registers, or the EDM bit of DBCR0 require m_clk to be running for proper operation. The
OnCE control register provides a means of signaling this need to a system level clock
control module via the OCR
In addition, since the CPU may cause multiple bits of certain registers to change state,
reads of certain registers while the CPU is running (DBSR, etc.) may not have consistent bit
settings unless read twice with the same value indicated. In order to guarantee that the
contents are consistent, the CPU should be placed into debug mode, or multiple reads
should be performed until consistent values have been obtained on consecutive reads.
Table 960
1706/2058
provides bit definitions for the OnCE Control Register.
Table 959. OCR field descriptions
WKUP
provides a list of access requirements for OnCE registers.
DocID027809 Rev 4
Description
, which must be set for FDB to take effect.
EDM
control bit.
RM0400