Table 402. Tcdsr Field Descriptions - STMicroelectronics SPC572L series Reference Manual

Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Interface
Offset 0x408
0 1
R
W
Reset 0 0
16 17
R
W
Reset 0 0
Field
0–31
DS_CH[x]
f Table 403. Test Channel DMA Select Registers to Channel Association
Parameter num_testch vector has positional inference for TCDSR such that num_testch(i)
(i = 0–31) corresponds to TCDSR bit[0:31]. If any of the num_testch(i) value is '0', the
corresponding bit is not implemented and read access returns '0' on that bit location.
If the complete num_testch is all 0's, TCDSR is not implemented and treated as reserved
space. Any attempt to access this space generates a transfer error.
36.5.1.24 Test Channel Normal Conversion Mask Register (TCNCMR)
The normal conversion mask register to channel association is described in
Offset 0x40C
0 1
R
W
Reset 0 0
16 17
R
W
Reset 0 0
Figure 352. Test Channel Normal Conversion Mask Register (TCNCMR)
792/2058
2 3 4 5
0 0 0 0
18 19 20 21
0 0 0 0
Figure 351. Test Channel DMA Select Register (TCDSR)

Table 402. TCDSR field descriptions

DMA select for channel x
0 CH[x] is disabled to transfer data in DMA mode.
1 CH[x] is enabled to transfer data in DMA mode.
Register
TCDSR
2 3 4 5
0 0 0 0
18 19 20 21
0 0 0 0
DocID027809 Rev 4
6 7 8 9
DS_CH[x]
0 0 0 0
22 23 24 25
DS_CH[x]
0 0 0 0
Description
6 7 8 9
NCE_CH[x]
0 0 0 0
22 23 24 25
NCE_CH[x]
0 0 0 0
Access: User Read/Write
10 11 12 13
0 0 0 0
26 27 28 29
0 0 0 0
Register bits 31:0
DS_CH[127:96]
Table
Access: User Read/Write
10 11 12 13
0 0 0 0
26 27 28 29
0 0 0 0
14 15
0 0
30 31
0 0
405.
14 15
0 0
30 31
0 0