Descriptor Group Lower Address Register (Galr) - STMicroelectronics SPC572L series Reference Manual

Fast Ethernet Controller (FEC)
Offset: 120h
0 1 2 3
R
W
Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
Figure 705. Descriptor Group Upper Address Register (GAUR)
Field
The GADDR1 register contains the upper 32 bits of the 64-bit hash table used in the address
GADDR1 recognition process for receive frames with a multicast address. Bit 31 of GADDR1 contains hash
index bit 63. Bit 0 of GADDR1 contains hash index bit 32.
48.4.17

Descriptor Group Lower Address Register (GALR)

GALR contains the lower 32 bits of the 64-bit hash table used in the address recognition
process for receive frames with a multicast address.
This register is not reset and you must initialize it.
Offset: 124h
0 1 2 3
R
W
Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
Figure 706. Descriptor Group Lower Address Register (GALR)
Field
The GADDR2 register contains the lower 32 bits of the 64-bit hash table used in the address
GADDR2 recognition process for receive frames with a multicast address. Bit 31 of GADDR2 contains hash
index bit 31. Bit 0 of GADDR2 contains hash index bit 0.
48.4.18 Transmit FIFO Watermark Register (TFWR)
The TFWR controls the amount of data required in the transmit FIFO before transmission of
a frame can begin. This allows you to minimize transmit latency (TFWR = 00 or 01) or allow
for larger bus access latency (TFWR = 11) due to contention for the system bus. Setting the
watermark to a high value minimizes the risk of transmit FIFO underrun due to contention
for the system bus. The byte counts associated with the TFWR field may need to be
modified to match a given system requirement (worst case bus access latency by the
transmit data DMA channel).
1316/2058
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Table 715. GAUR field descriptions
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Table 716. GALR field descriptions
DocID027809 Rev 4
GADDR1
Description
GADDR2
Description
RM0400
Access: User read/write
Access: User read/write