Introduction - STMicroelectronics SPC572L series Reference Manual

RM0400
59 JTAG Controller (JTAGC)
59.1

Introduction

The JTAGC block provides the means to test chip functionality and connectivity while
remaining transparent to system logic when not in test mode. Testing is performed via a
boundary scan technique, as defined in the IEEE 1149.1-2001 standard. All data input to
and output from the JTAGC block is communicated in serial format.
59.1.1 Block Diagram
The following is a block diagram of the JTAG Controller (JTAGC) block.
JCOMP
TMS
TCK
TDI
Figure 1020. JTAG (IEEE 1149.1) block diagram
1-bit Bypass Register
32-bit Device Identification Register
Boundary Scan Register
TAP Instruction Decoder
TAP Instruction Register
DocID027809 Rev 4
Test Access Port (TAP)
Controller
JTAG Controller (JTAGC)
1731/2058
TDO
1742