Instruction/Data Prefetch Triggering - STMicroelectronics SPC572L series Reference Manual

Flash memory controller (PFLASH Controller)
In order for prefetching to occur, PFCR1[P0_BFEN] must be set to '1', PFCR1[P0_PFLIM]
must be non-zero, and either PFCR1[P0_IPFEN] or PFCR1[P0_DPFEN] must be asserted.
Refer to
description of these controls.
28.5.9

Instruction/Data prefetch triggering

Port0 prefetch triggering may be enabled for instruction reads via the PFCR1[IPFEN] control
field, while Port0 prefetching for data reads is enabled via the PFCR1[DPFEN] control field.
Additionally, the PFCR1[PFLIM] must also be set to enable prefetching on Port0. Refer to
Section 28.4.1.1, Platform Flash Configuration Register 1 (PFCR1)
these controls. Prefetches are never triggered by write cycles.
28.5.10 Per-Master prefetch triggering
Prefetch triggering may be controlled for individual bus masters. Refer to
Platform Flash Configuration Register 1 (PFCR1)
28.5.11 Buffer allocation
Allocation of the line read buffers is controlled via the PFCR3 control register, specifically
the line buffer configuration (P0_WCFG) field. Refer to
Configuration Register 3
resources (with both ways within a given set) or with a fixed partition between ways
allocated to instruction or data accesses. For the fixed partitions, ways 0 is allocated for
instruction fetches and way1 for data accesses.
28.5.12 PFlash calibration remap support
The flash memory controller supports calibration development by providing a remapping
function to route flash accesses to overlay RAM. Recall this family of devices includes a
comprehensive set of features including dedicated overlay RAM arrays to aid calibration
and debug. The overlay function supports the following features:
•
Can be mapped over internal flash memory
–
•
Can be used to hold device debug trace stream
–
• Protected with error detection and correction mechanism
•
Accesses to all overlay RAMs can have the same timing as accesses to internal flash
–
•
Support for up to 32 distinct calibration remap regions.
The calibration remap function supports up to two different overlay RAM targets:
1. An internal overlay RAM is included on all standard production devices.
2. A portion of the system RAM can be used for overlay.
where the overlay RAM is selected based on the translated physical address.
582/2058
Section 28.4.1.1, Platform Flash Configuration Register 1 (PFCR1)
(PFCR3). The buffers can be organized as a "pool" of available
Allows calibration of constant data without requirement for additional external
RAMs and calibration memory interfaces
Allows limited trace based debug without requirement for complex debug tool
hardware and access to high speed trace port
Timing for calibration accesses to a particular overlay RAM is only guaranteed if it
is not being used as a destination for trace streaming at the same time
for a description of these controls.
DocID027809 Rev 4
for a
for a description of
Section 28.4.1.1,
Section 28.4.1.2, Platform Flash
RM0400