Table 371. Msr Field Descriptions - STMicroelectronics SPC572L series Reference Manual

Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Interface
Field
Reserved
0–3
Write of any value has no effect; read value is always 0.
This status bit is used to signal that a normal conversion is ongoing.
4
0 Normal conversion is not taking place.
NSTART 1 Normal conversion is ongoing or the normal conversion is pending due to injected conversion
or CTU triggered injected conversion.
Reserved
5–7
Write of any value has no effect; read value is always 0.
This status bit is used to signal that an injected conversion is ongoing.
8
0 Injected conversion is not taking place.
JSTART
1 Injected conversion is ongoing.
Reserved
9–12
Write of any value has no effect; read value is always 0.
This status bit is used to signal that an Injected conversion chain has been aborted. This bit is
13 reset when a new conversion starts.
JABORTCHAIN 0 Last injected conversion chain has not been aborted.
1 Last injected conversion chain has been aborted.
Reserved
14
Write of any value has no effect; read value is always 0.
15 Reserved
16–23
Channel under measure address
This status bit is used to signal which channel is under measure.
CHADDR[7:0]
24–28 Reserved
The value of this parameter depends on ADC status. While requesting an external
channel conversion, SARADC digital interface needs to wait for a fixed time determined by
DSD bitfield of DSDR before proceeding to actual sampling phase.
This is known as wait state.
000 IDLE
29–31
001 Power-down
ADCSTATUS[2:0]
010 Wait state
011 —
100 Sample
101 —
110 Conversion
111 —
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Table 371. MSR field descriptions

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