Channel Configuration Register (Dmamux_Chcfgn) - STMicroelectronics SPC572L series Reference Manual

Direct Memory Access Multiplexer (DMAMUX)
Absolute
address
(hex)
5 Channel Configuration register (DMAMUX_CHCFG5)
6 Channel Configuration register (DMAMUX_CHCFG6)
7 Channel Configuration register (DMAMUX_CHCFG7)
8 Channel Configuration register (DMAMUX_CHCFG8)
9 Channel Configuration register (DMAMUX_CHCFG9)
A Channel Configuration register (DMAMUX_CHCFG10)
B Channel Configuration register (DMAMUX_CHCFG11)
C Channel Configuration register (DMAMUX_CHCFG12)
D Channel Configuration register (DMAMUX_CHCFG13)
E Channel Configuration register (DMAMUX_CHCFG14)
F Channel Configuration register (DMAMUX_CHCFG15)
20.3.1

Channel Configuration register (DMAMUX_CHCFGn)

Each of the DMA channels can be independently enabled/disabled and associated with one
of the DMA slots (peripheral slots or always-on slots) in the system.
Note: Setting multiple CHCFG registers with the same source value will result in unpredictable
behavior.
Note: Before changing the trigger or source settings, a DMA channel must be disabled via
CHCFGn[ENBL].
Address: 0h base + 0h offset + (1d × i), where i=0d to 15d
0
R
ENBL
W
Reset 0
Figure 157. Channel Configuration register (DMAMUX_CHCFGn)
452/2058
Table 206. DMAMUX memory map(Continued)
Register name
1 2
TRIG
0 0
DocID027809 Rev 4
Width
(in bits)
8
8
8
8
8
8
8
8
8
8
8
3 4
SOURCE
0 0
Reset Section/
Access
value
R/W 00h 20.3.1/452
R/W 00h 20.3.1/452
R/W 00h 20.3.1/452
R/W 00h 20.3.1/452
R/W 00h 20.3.1/452
R/W 00h 20.3.1/452
R/W 00h 20.3.1/452
R/W 00h 20.3.1/452
R/W 00h 20.3.1/452
R/W 00h 20.3.1/452
R/W 00h 20.3.1/452
Access: User read/write
5 6
0 0
RM0400
page
7
0