RM0400
In slave mode, the parity is controlled by the PE and PP bits of the CTAR0 register similar to
the master mode parity generation without continuous PCS selection.
46.5.11.2 Parity for DSI frames
When DSPI is in Master Mode, parity generation is controlled by PE and PP bits of the
DSPI_DSICR0 register similar to the SPI frames. The parity is calculated and checked for
each DSI frame. (DSPI_DSICR0[DCONT] bit has no effect on parity generation. In slave
mode, the parity is controlled by the PE and PP bits of the CTAR1 register.
If the parity error occurs for received DSI frame, the DSPI_SR[DPEF] bit is set. If
DSPI_DSICR0[PES] bit is set, the DSPI stops DSI frames transmission. To resume DSI
operation, clear the DSPI_SR[DPEF] or the DSPI_DSICR0[PES] bits.
46.5.12
Interrupts/DMA requests
Certain DSPI conditions can generate only interrupt requests and other DSPI conditions can
generate either interrupt requests or DMA requests.
End of Queue (EOQ)
TX FIFO Fill
CMD FIFO Fill
TX FIFO Invalid Write
Transfer Complete
CMD Transfer Complete
SPI Transfer Complete
DSI Transfer Complete
TX FIFO Underflow
RX FIFO Drain
RX FIFO Overflow
SPI Parity Error
DSI Parity Error
DSI Deserialized Data Match
Each condition has a flag bit in the DSPI Status Register (SR) and a Request Enable bit in
the DSPI DMA/Interrupt Request Select and Enable Register (RSER). The TX FIFO Fill
Flag (TFFF) and RX FIFO Drain Flag (RFDF) generate interrupt requests or DMA requests
depending on the TFFF_DIRS and RFDF_DIRS bits in the RSER.
The DSPI module also provides a global interrupt request line, which is asserted when any
of individual interrupt requests lines is asserted.
Table 650. Interrupt and DMA request conditions
DSPI condition
DocID027809 Rev 4
Deserial Serial Peripheral Interface (DSPI)
Table 650
lists these conditions.
Flag
Interrupt
EOQF
Yes
TFFF
Yes
CMDFFF
Yes
TFIWF
Yes
TCF
Yes
CMDTCF
Yes
SPITCF
Yes
DSITCF
Yes
TFUF
Yes
RFDF
Yes
RFOF
Yes
SPEF
Yes
DPEF
Yes
DDIF
Yes
Request type
DMA
—
Yes
Yes
—
—
—
—
—
—
Yes
—
—
—
—
1211/2058
1220
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