Table 116. Siul2_Disr0 Field Descriptions - STMicroelectronics SPC572L series Reference Manual

System Integration Unit Lite2 (SIUL2)
Field
ASCII character in MCU Part Number:
16–23 0x4CL
FAMILYNUM
All other values reserved for future use.
24–31 Reserved
13.2.2.3 SIUL2 DMA/Interrupt Status Flag Register 0 (SIUL2_DISR0)
The DMA/Interrupt Status Register contains flag bits that record an event on the external
IRQ pins. When an event as defined in IRQ Rising-Edge Event Enable Register
(SIUL2_IREER0) and IRQ Falling-Edge Event Enable Register (SIUL2_IFEER0) occurs,
the corresponding flag bit is set. The IRQ Flag bit is set irrespective of the corresponding
DMA/Interrupt Request Enable bit in DMA/Interrupt Request Enable Register
(SIUL2_DIRER0) is enabled. The EIF bit remains set until cleared by software or through
the servicing of a DMA request. The EIF bits are cleared by writing a '1' to the bits. A write of
'0' has no effect.
This register contains the interrupt flags.
Address: 0x0010
0 1
R 0 0
W
Reset 0 0
16 17
R 0 0
W
Reset 0 0
Figure 56. SIUL2 DMA/Interrupt Status Flag Register (SIUL2_DISR0)
Field
0–20 Reserved
External Interrupt Status Flag x—This flag can be cleared only by writing 1. Writing 0 has no
21 effect. If enabled (SIUL2_DIRER[x]), EIF[x] causes an interrupt or DMA request.
EIF10 0 No interrupt or DMA event has occurred on the pad
1 An interrupt or DMA event as defined by SIUL2_IREER[x] and SIUL2_IFEER[x] has occurred
22–25 Reserved
External Interrupt Status Flag x—This flag can be cleared only by writing 1. Writing 0 has no
26 effect. If enabled (SIUL2_DIRER[x]), EIF[x] causes an interrupt or DMA request.
EIF5 0 No interrupt or DMA event has occurred on the pad
1 An interrupt or DMA event as defined by SIUL2_IREER[x] and SIUL2_IFEER[x] has occurred
290/2058
Table 115. SIUL2_MIDR2 field description(Continued)
2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
EIF
0 0 0
10
w1c
0 0 0 0

Table 116. SIUL2_DISR0 field descriptions

DocID027809 Rev 4
Description
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
0 0 0 0
0 0 0 0
Description
Access: User read/write
10 11 12 13
0 0 0 0
0 0 0 0
26 27 28 29
EIF5 0 EIF3 EIF2 EIF1 EIF0
w1c w1c w1c
0 0 0 0
RM0400
14 15
0 0
0 0
30 31
w1c w1c
0 0