Features - STMicroelectronics SPC572L series Reference Manual

Error Injection Module (EIM)
33.1.2

Features

The EIM includes these features:
•
supports up to six error injection channels
•
protection against accidental enable and reconfiguration error injection function via
two-stage enable mechanism
33.2 Memory map and register definition
The EIM module provides an IPS programming model mapped to a standard 16 KB on-
platform peripheral slot. The programming model can only be referenced using a 32-bit
(word) access. Attempted references using different access sizes or to undefined (reserved)
addresses or in user mode generates an IPS error termination. The EIM allows access to
the programming model by all system bus masters.
The programming model can only be accessed in supervisor mode.
Attempted updates to the programming model while the EIM module is in the midst of an
operation will result in non-deterministic behavior.
33.2.1 Memory map
Address
offset
Error Injection Module Configuration Register
0x000
(EIMCR)
0x004 Error Injection Channel Enable Register (EICHEN)
0x00A–0x0FF
Error Injection Channel0 Descriptor, Word0
0x100
(EICHD0.Word0)
Error Injection Channel0 Descriptor, Word1
0x104
(EICHD0.Word1)
Error Injection Channel0 Descriptor, Word2
0x108
(EICHD0.Word2)
0x10C–0x1FF
Error Injection Channel1 Descriptor, Word0
0x200
(EICHD1.Word0)
Error Injection Channel1 Descriptor, Word1
0x204
(EICHD1.Word1)
Error Injection Channel1 Descriptor, Word2
0x208
(EICHD1.Word2)
0x20C–0x2FF
Error Injection Channel2 Descriptor, Word0
0x300
(EICHD2.Word0)
684/2058
Table 333. EIM memory map
Register
Reserved
Reserved
Reserved
DocID027809 Rev 4
Access Reset value
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
RM0400
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