Figure 241. Pfcr3 Register - STMicroelectronics SPC572L series Reference Manual

RM0400
Field
29–30
P0_PFLIM
31
P0_BFEN
28.4.1.2 Platform Flash Configuration Register 3 (PFCR3)
.
0 1
16 17 18
0 1
R
P0_WCFG
W
Reset 0 0
16 17 18
R 0
W
Reset 0 0
Table 284. PFCR1 field descriptions(Continued)
Port0 PFlash Prefetch Limit. This field controls the prefetch algorithm used by the prefetch
controller. This field defines a limit on the maximum number of sequential prefetches which
will be attempted between buffer misses. In all situations when enabled, only a single
prefetch is initiated on each buffer miss or hit.
This field is cleared by hardware reset.
00 No prefetching or buffering is performed.
01 The referenced line is prefetched on a buffer miss, that is, prefetch on miss.
1x The referenced line is prefetched on a buffer miss, or the next sequential line is
prefetched on a buffer hit (if not already present), that is, prefetch on miss or hit.
Port0 PFlash Line Read Buffers Enable. This bit enables or disables line read buffer hits. It
is also used to invalidate the buffers. This bit is cleared by hardware reset.
0 The line read buffers are disabled from satisfying read requests, and all buffer valid bits
are cleared.
1 The line read buffers are enabled to satisfy read requests on hits. Buffer valid bits may be
set when the buffers are successfully filled.
2 3 4 5
19 20 21
2 3 4 5
0 0 0 0
0 0 0 0
19 20 21
0 0 0 0
0 0 0 0

Figure 241. PFCR3 register

DocID027809 Rev 4
Flash memory controller (PFLASH Controller)
Description
6 7 8 9
22 23 24 25
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
0 0 0 0
0 0 0 0
10 11 12 13
26 27 28 29
10 11 12 13
0 0 0 0
0 0 0 0
26 27 28 29
0 0 0 0
0 0 0 0
14 15
30 31
14 15
0
0 0
30 31
0 0
0 0
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