Interrupt Definitions - STMicroelectronics SPC572L series Reference Manual

Core e200z215An3 description
0 1 2 3 4 5 6
The IVPR fields are defined in
Bit(s) Name
Vector Base
This field is used to define the base location of the vector table, aligned to a 256 byte
boundary. This field provides the high-order 24 bits of the location of all interrupt handlers
0:23
Vector
(unless hardware vectoring is used). The vector offset value appropriate for the type of
Base
(32:55) exception being processed is concatenated with the IVPR Vector Base to form the address of
the handler in memory. For hardware-vectored interrupts, the value of the supplied interrupt
vector is logically OR'ed with the low order bits of the Vec Base Field to determine the
interrupt handler address.
24:31
— Reserved
(56:63)
12.6.5

Interrupt Definitions

12.6.5.1 Critical Input Interrupt (offset 0x00)
A Critical Input exception is signaled to the processor by the assertion of the critical interrupt
pin. If the exception is enabled by MSR
A Critical Input interrupt may be delayed by other higher priority exceptions or if MSR
cleared when the exception occurs.
Table 99
Register
Set to the effective address of the instruction that the processor would have attempted to execute next
CSRR0
if no exception conditions were present.
CSRR1 Set to the contents of the MSR at the time of the interrupt
SPV 0
WE 0
MSR CE 0
EE 0
PR 0
ESR Unchanged
MCSR Unchanged
DEAR Unchanged
IVPR || 0x00 (autovectored)
0:23
Vector
IVPR || (IVPR
0:15
274/2058
Vector Base
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SPR 63; Read/Write
Figure 52. Zen Interrupt Vector Prefix Register (IVPR)
Table 98. IVPR field descriptions
lists register settings when a Critical Input interrupt is taken.
Table 99. Critical Input Interrupt—register settings
FP
ME
FE0
DE
| p_voffset[0:13]) || 2'b00 (non-autovectored)
16:29
DocID027809 Rev 4
Table 98.
Description
, the Critical Input interrupt is taken.
CE
Setting description
0
—
0
(1)
—/0
0
FE1 0
IS 0
DS 0
PMM 0
RI —
RM0400
is
CE