Table 816. Master Node — Tx Mode — Register Setting - STMicroelectronics SPC572L series Reference Manual

LINFlexD
Table 816
frame.
LIN frame
Master to Slave
Slave to Master
Slave to Slave
The concept FSM to control the DMA Tx interface is given in
moves to Idle state immediately at next clock edge if DMATXE[0] = 0. The TCD setting
(word transfer) is given in
halfword or byte transfer are allowed.
TCD field
CITER[14:0]
BITER[14:0]
NBYTES[31:0]
SADDR[31:0]
SOFF[15:0]
SSIZE[2:0]
SLAST[31:0]
DADDR[31:0]
DOFF[15:0]
DSIZE[2:0]
DLAST_SGA[31:0]
INT_MAJ
D_REQ
START
1442/2058
provides the register settings of the LINCR2 and BIDR for each class of LIN
Table 816. Master node — Tx mode — Register setting
Table
Table 817. TCD setting — Master node — Tx mode
Value
1 Single iteration for the major loop
1 Single iteration for the major loop
Data buffer is filled with dummy bytes if length is not word-aligned
[4 + 4] + 0/4/8 = N
LINCR2 + BIDR + BDRL + BDRM
— RAM address
4 Word increment
2 Word transfer
–N —
— LINCR2 address
4 Word increment
2 Word transfer
–N No scatter/gather processing
0/1 Interrupt disabled/enabled
1 Only on the last TCD of the chain
0 No software request
LINCR2
DDRQ = 1
DTRQ = 0
HTRQ = 0
DDRQ = 0
DTRQ = 0
HTRQ = 0
DDRQ = 1
DTRQ = 0
HTRQ = 0
817. All other TCD fields = 0. TCD settings based on
DocID027809 Rev 4
BIDR
DFL = payload size
ID = address
CCS = checksum
DIR = 1 (TX)
DFL = payload size
ID = address
CCS = checksum
DIR = 0 (RX)
DFL = payload size
ID = address
CCS = checksum
DIR = 0 (RX)
Figure 832. DMA TX FSM
Description
RM0400