Embedded Flash Memory (Mp55) - STMicroelectronics SPC572L series Reference Manual

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Embedded Flash Memory (MP55)

29.1 Introduction
The Flash Memory module serves as electrically programmable and erasable nonvolatile
memory, for instructions and data storage.
The Flash Memory module is a nonvolatile, solid-state silicon memory device consisting of
blocks of single transistor storage elements, an electrical means for selectively adding
(programming) and removing (erasing) charge from these elements, and a means of
selectively sensing (reading) the charge stored in these elements.
The Flash Memory module has two functional units:
•
The Flash core. which is composed of a common high voltage HV block and a Flash
array which can contain one or more Flash partitions. Each Flash partition is composed
of arrayed nonvolatile storage elements, sense amplifiers, row decoders and column
decoders. The arrayed storage elements in the Flash partitions are subdivided into
physically separate units referred to as blocks.
• The Memory interface. Containing the registers and logic which control the operation
of the Flash core and contains two main ports: the Array Interface and the Registers
Interface. The memory interface is also the interface between the Flash Memory
module and a Bus Interface Unit (BIU) and contains the ECC and redundancy logic.
A BIU connects the Flash Memory module to a system bus, and contains all the system
level customization required for the SoC application. The Flash Memory module is generic
and requires a BIU to configure it for different SoC applications. A BIU is not included.
29.1.1 Overview
The 1584 KB Flash Memory module contains 2 array partitions. Read-While-Write
operations are only possible for seperate partitions, meaning fetching/reading from one (or
more) partition(s) while a program/erase operation is active on one other partition. Each
module counts as an RWW partition.
EEPROM emulation is managed in 1 of the modules, referred to as Data Flash.
The Modify operations are managed by an embedded Flash Program/Erase Controller
(FPEC). Commands to the FPEC are delivered through a User Registers interface.
The Read Data bus is 128 bits wide, while the Flash registers are on a separate, 32-bit bus.
The high voltages needed for Program and Erase operations are internally generated and
are common for the 2 partitions.
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