Memory Map And Register Description - STMicroelectronics SPC572L series Reference Manual

Serial Interprocessor Interface (SIPI)
Write Transfer Control
Single Write Transfer Address
Single Write Transfer Value
Multiple Write Transfer Address
Multiple Write Transfer Count
Multiple Write Transfer Value
45.15

Memory map and register description

Offset from
SIPI base
(hex)
0000
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028
002C
0030
1118/2058
Figure 568. SIPI control & status overview – Register transfer
SIPI Channel 0 - 3
Transfer Command
Acknowledge Headers
Table 593. SIPI memory map
SIPI Channel Control Register 0 (SIPI_CCR0)
SIPI Channel Status Register 0 (SIPI_CSR0)
Reserved
SIPI Channel Interrupt Register 0 (SIPI_CIR0)
SIPI Channel Timeout Register 0 (SIPI_CTOR0)
SIPI Channel CRC Register 0 (SIPI_CCRC0)
SIPI Channel Address Register 0 (SIPI_CAR0)
SIPI Channel Data Register 0 (SIPI_CDR0)
SIPI Channel Control Register 1 (SIPI_CCR1)
SIPI Channel Status Register 1 (SIPI_CSR1)
Reserved
SIPI Channel Interrupt Register 1 (SIPI_CIR1)
SIPI Channel Timeout Register 1 (SIPI_CTOR1)
Channel Status
Channel Error
Channel Control
Time Out Check
Register
DocID027809 Rev 4
Read Transfer Control
Single Read Transfer Address
Single Read Transfer Value
Multiple Read Transfer Address
Multiple Read Transfer Count
Multiple Read Transfer Value
Transfer Read Configuration
Section/Page
Section 45.15.1.1
Section 45.15.1.2
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Section 45.15.1.3
Section 45.15.1.4
Section 45.15.1.5
Section 45.15.1.6
Section 45.15.1.7
Section 45.15.1.1
Section 45.15.1.2
—
Section 45.15.1.3
Section 45.15.1.4
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