Figure 681. Tx Lvds Loopback (External) Mode With Automatic Frame Generation - STMicroelectronics SPC572L series Reference Manual

LVDS Fast Asynchronous Serial Transmission (LFAST) – Interprocessor Communications

Figure 681. Tx LVDS Loopback (external) mode with automatic frame generation

RXDATA_P
RXDATA_N
TXDATA_P
TXDATA_N
Entry to Tx LVDS loopback with automatic frame generation mode:
1. S/W programs TMCR[LPMOD] = 100b.
2. Loopback can be turned on by either of the following methods:
–
–
Exit from Tx LVDS Loopback with automatic frame generation mode can be done by the
following method:
•
S/W programs TMCR[LPON] = 0.
47.7.7.2 Clock test mode
The bit TMCR[CLKTST] enables or disables the Clock Test mode of the LFAST module. In
this mode the LFAST sends fixed pattern out on the LD at the current configured RxData
clock rate. It is a RWM bitfield and the default setting is 0 (off). This bit can be set under one
of the following conditions:
•
S/W programs TMCR[CLKTST].
•
For Slave Only: Reception of ICLC frame with payload 34h (Clock Test mode on) from
LFAST Master.
The Tx Controller will send out a pattern of alternating 1 and 0 (pattern 101010...). This
provides a divide by 2 test clock of the current Tx clock.
The Clock Test mode can be cancelled by any of the following methods:
• S/W programs TMCR[CLKTST] = 0.
•
For LFAST Slave: Reception of ICLC frame with payload 38h (Test mode off) from
LFAST Master.
In clock test mode the Tx Controller does not output any synchronization pattern or header,
just a pattern of alternating 1's and 0's.
1282/2058
LR
LD
S/W programs TMCR[LPON] = 1.
For Slave Only: Reception of ICLC frame with payload FFh (Loopback mode on)
from LFAST Master
DocID027809 Rev 4
Rx CONTROLLER
TMCR[LPMOD] = TX LVDS LOOPBACK
Tx CONTROLLER
CSR
RX FIFO
CSR
TX FIFO
AUTOMATIC FRAME