Table 549. Rx Fifo 0 Configuration Register Field Descriptions - STMicroelectronics SPC572L series Reference Manual

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Table 549. Rx FIFO 0 Configuration register field descriptions

Field
0 Reserved
Rx FIFO 0 Watermark
1:7
0 Watermark interrupt disabled
1-64 Level for Rx FIFO 0 watermark interrupt (IR[RF0W])
F0WM
>64 Watermark interrupt disabled
8:9 Reserved
Rx FIFO 0 Size
0 No Rx FIFO 0
10:15
1-64 Number of Rx FIFO 0 elements
F0S
>64 Values greater than 64 are interpreted as 64
The Rx FIFO 0 elements are indexed from 0 to F0S-1
16:29 Rx FIFO 0 Start Address
Start address of Rx FIFO 0 in Message RAM (32-bit word address,
F0SA
30:31 Reserved
44.3.5.2.26 Rx FIFO 0 Status Register (RXF0S)
Address: 0x00A4
0 1
R 0 0
W
0 0
16 17
R 0 0
W
0 0
Field
0:5 Reserved
Rx FIFO 0 Message Lost
6 This bit is a copy of interrupt flag IR[RF0L]. When IR[RF0L] is reset, this bit is also reset.
RF0L 0 No Rx FIFO 0 message lost
1 Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero
Rx FIFO 0 Full
7
0Rx FIFO 0 not full
F0F
1Rx FIFO 0 full
8:9 Reserved
2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
F0GI
0 0 0 0
Table 550. Rx FIFO 0 Status Register
Table 551. Rx FIFO 0 Status register field descriptions
DocID027809 Rev 4
Description
6 7 8 9
RF0
F0F 0 0
L
0 0 0 0
22 23 24 25
0
0 0 0 0
Description
CAN Subsystem
Figure 514).
10 11 12 13
F0PI
0 0 0 0
26 27 28 29
F0FL
0 0 0 0
Access: R
14 15
0 0
30 31
0 0
1033/2058
1091