Features; Memory Map And Register Definition; Memory Map - STMicroelectronics SPC572L series Reference Manual

RM0400
16.3

Features

The SMPU feature set includes:
•
Supports up to 24 program-visible 128-bit region descriptors, accessible as four 32-bit
words each. (Specific module instances may support fewer than 24).
–
–
–
–
–
•
Supports as many as eight crossbar slave ports
•
Detects access errors if a memory reference does not hit in any memory region, or if
the reference is illegal in all hit memory regions. If an access error occurs, the
reference is terminated with an error response, and the SMPU inhibits the bus cycle
being sent to the targeted slave device.
•
Aborted core accesses generate instruction storage (ISI) or data storage (DSI)
interrupts (see the documentation related to the core for details).
•
Error registers (per bus master ID) capture the last faulting address, attributes, and
other information.
•
Global SMPU enable/disable control bit
16.4

Memory map and register definition

16.4.1

Memory map

The programming model is partitioned into three groups: control registers, error capture
registers, and the data structure containing the region descriptors.
The programming model can only be referenced using 32-bit accesses. Attempted
references using different access sizes, to undefined (reserved) addresses, or with a non-
supported access type (a write to a read-only register, or a read of a write-only register)
generate an error termination.
The programming model can be accessed only in supervisor mode.
Note: See the device configuration details for any chip-specific register information for this
module. For example, a specific instance of a module may support only up to eight region
descriptors.
Each region descriptor defines an arbitrarily sized space, aligned anywhere in
memory
– Region sizes can vary from a minimum of 1 byte to a maximum of (4
GB minus 1 byte)
Read/write access control permissions defined in region descriptor
Cache-inhibit attribute indicator per region descriptor
Hardware-assisted maintenance of the descriptor valid bit minimizes coherency
issues
Priority given to granting permission over denying access for overlapping region
descriptors
DocID027809 Rev 4
System Memory Protection Unit (SMPU)
327/2058
344