Table 1028. Spu Action Decoder - STMicroelectronics SPC572L series Reference Manual

RM0400
Field
1 Reserved
31–2 Reserved
63.5.1.6 SLU action unit registers
The action unit of the SPU is responsible for generating the action triggers supported by
various actions, listed in <Cross Refs>Section 63.2, SPU
mapped to the events by programming the action registers. Each event can be programmed
to trigger interrupts, watchpoints, trace signals, counter stop/reset/increment and many
other general actions.
in three groups: client based, counter based, system related.
Group bit
Client/counter bit [9:5]
[11:10]
ID Name ID
00000
00001
00010
00011–00111
01000
01001–01111
10000
Client
00
10001
group
10010–10111
11000
11001–11110
11111
00000
00001
00010
Counter
01
group
...
01111
10000–11111
Table 1027. SE register field descriptions(Continued)
Table 1028

Table 1028. SPU action decoder

Name ID
Reserved 0000
Reserved —
CPU2 0010
Reserved 0011
GTM 0100
Reserved 0101
Reserved 0110
Reserved 0111
Reserved 1000
NAR 1001
1010
Reserved 1011
1100
Trace
1101–1111 Reserved
(1)
group
Counter0 0000
Counter1 0001
Counter2 0010
... 0011
Counter15 0100
Reserved 0101–1111 Reserved
DocID027809 Rev 4
Description
shows the bit mapping for all the possible actions divided
Action bit [4:1]
Name
No action
—
OTM/gtm_gen1 trace
PTM/gtm_gen2 trace
WTM/gtm_gen3 trace
NAR_supp_trig1
NAR_supp_trig2
NAR_supp_trig3
NAR_supp_trig4
GTM_dtm_tr0
GTM_dtm_tr1
GTM_ftm_tr0
GTM_ftm_tr1
No action
Start timer/Incr counter
Stop timer
Reset counter
Capture
Sequence Processing Unit (SPU)
actions. The action triggers are
Comment
—
Valid for Cores,,
GTM and trace
group actions.
Valid for NAR as
the suppress
trigger actions
Valid for GTM
Valid for CPU
cores
—
Valid for all
counters/timers
Enable bit
[0]
0=Stop
1=Start
For NAR
suppress
trigger =
Don't care
0=Stop
1=Start
Don't care
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