Register Definition - STMicroelectronics SPC572L series Reference Manual

RM0400
61.3

Register definition

Table 998
bit accesses are valid. The effects of access that are not 32 bits are not defined.
Address offset
(hex)
0x0 Module Configuration Register (JDC_MCR)
0x4 Module Status Register (JDC_MSR)
0x8 JTAG Output Data Register (JDC_JOUT_IPS)
0xC JTAG Input Data Register (JDC_JIN_IPS)
61.3.1 Register descriptions
61.3.1.1 Module configuration register (JDC_MCR)
Figure 1046
the JDC. This register is reset by system destructive reset.
Address: 0x00
0 1
R 0 0
W
Reset 0 0
16 17
R 0 0
W
Reset 0 0
The JDC_MCR is described in
Field
JIN Interrupt Enable.
JIN_IEN
0 Setting of JDC_MSR[JIN_INT] bit does not assert the JIN interrupt
1 Setting of JDC_MSR[JIN_INT] bit asserts the JIN interrupt
JOUT Interrupt Enable.
JOUT_IEN
0 Setting of JDC_MSR[JOUT_INT] bit does not assert the JOUT interrupt
1 Setting of JDC_MSR[JOUT_INT] bit asserts the JOUT interrupt
shows the JDC module registers. Four 32-bit registers are implemented. Only 32-
Table 998. JDC memory map
Register
shows the JDC_MCR.The JDC_MCR is used to enable the interrupt outputs of
2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
0 0 0 0
0 0 0 0
Figure 1046. Module Configuration Register (JDC_MCR)
Table 999. JDC_MCR register field descriptions
DocID027809 Rev 4
Access
Read Only
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
0 0 0 0
0 0 0 0
Table 999.
Description
JTAG Data Communication (JDC)
Reset value
R/W 0x0000_0000
W1C 0x0000_0000
R/W 0x0000_0000
0x0000_0000
Access: User read/write
10 11 12
0 0 0
0 0 0
26 27 28
0 0 0
0 0 0
Section/page
61.3.1.1/1797
61.3.1.2/1798
61.3.1.3/1798
61.3.1.4/1799
13 14 15
0 0
0 0 0
29 30 31
0 0
0 0 0
1797/2058
1802