Interface Options - STMicroelectronics SPC572L series Reference Manual

RM0400
48.2.2

Interface options

The following interface options are supported. A detailed discussion of the interface
configurations is provided in
48.2.2.1 10 Mbps and 100 Mbps MII interface
The IEEE 802.3 standard defines the media independent interface (MII) for 10/100 Mbps
operation. The MAC-PHY interface may be configured to operate in MII mode by
programming RCR[MII_MODE] = 1.
The operation speed is determined by the FEC_TXCLK and FEC_RXCLK pins driven by the
external transceiver. The transceiver auto-negotiates the speed or software controls it via
the serial management interface (FEC_MDC/FEC_MDIO pins) to the transceiver. Refer to
the MMFR and MSCR register descriptions, as well as the section on the MII, for a
description of how to read and write registers in the transceiver via this interface.
48.2.2.2 10 Mbps and 100 Mbps RMII interface
The reduced media independent interface (RMII) is a low-cost alternative to the IEEE 802.3
MII standard. This interface provides the functionality of the MII interface on a total of 8 pins
instead of 18. The RMII interface for 10/100 Ethernet MAC-PHY interface was defined by an
industry consortium and is not currently included in the IEEE 802.3 standard. This
functionality is selected as described in the chip configuration chapter, and is reflected in the
read-only RCR[RMII_MODE] bit. The RCR[RMII_10T] bit determines the speed of
operation. The reference clock for RMII is always 50 MHz, but this clock can be divided by
10 within the RCR register to support 10 Mbps operation. The PHY must be configured
accordingly.
48.2.2.3 10 Mbps 7-wire interface operation
The FEC supports 7-wire interface used by many 10 Mbps Ethernet transceivers. The
RCR[MII_MODE] bit controls this functionality. If this bit is cleared, MII mode is disabled and
the 10 Mbps 7-wire mode is enabled.
48.2.3 Address recognition options
The address options supported are:
•
Promiscuous
•
Broadcast reject
•
Individual address (hash or exact match)
•
Multicast hash match
Address recognition options are discussed in detail in
recognition.
48.2.4 Internal loopback
Internal loopback mode is selected via RCR[LOOP]. Loopback mode is discussed in detail
in Section 48.5.16: MII internal and external
q. Interface selection is chip-specific; see the chapter that describes how modules are configured and connected.
(q)
Section 48.5.8: Network interface
DocID027809 Rev 4
Fast Ethernet Controller (FEC)
options.
Section 48.5.11: Ethernet address
loopback.
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