Low Voltage Requirement During Crank - STMicroelectronics SPC572L series Reference Manual

Power management
Warning:
Note: When supply falls below the internal power-on state detector threshold, the device
automatically resets and LVD270 is re-enabled.
On internal power-on signal assertion, all analog modules reach their safe state.
9.6.4

Low voltage requirement during crank

The device can continue operation to the minimum input voltage during crank.
In order to proceed with execution during cranking and prevent device reset, it is important
to correctly configure the high voltage LVDs.
During device switch-off, external LVD monitoring may not be activated quickly enough
(external assertion of the PORST pin) to avoid the −10% level being crossed before POR is
asserted. Malfunction is possible in this case, but reliability is not impacted and flash is not
corrupted.
Internal LVDs that monitor the supply ensure that the flash content is protected.
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LVD270 monitors can be disabled for test purposes via
software access of the PMC_REE register. However, the
internal monitors of the device may not detect that VDD_HV
voltage is outside functional range (below LVD270 threshold)
so the user must ensure a reset state by assertion of the
external PORST pin.
DocID027809 Rev 4
RM0400