Decorated Stores: St[B,H,W]D{Cb}X Rs,Rb,Ra - STMicroelectronics SPC572L series Reference Manual

Decorated Storage Memory Controller (DSMC)
30.3

Decorated Stores: st[b,h,w]d{cb}x rS,rB,rA

The next sections present descriptions of the specific operations, based on the 4-bit
command field defined in decoration[0:3]. These descriptions include the bit pattern
definitions for the 32-bit decoration value and include pseudo-code detailing the sequence
of operations. The decoration formats are defined using a <command>.<size> syntax
where the operand size specifier is b (byte, 8-bit), h (halfword, 16-bit) or w (word, 32-bit).
The operand size is specified directly in the decorated instruction executed in the core, and
this attribute is driven to the system bus as part of the decorated data transfer. Additionally,
the write data is taken from the right-justified 8, 16 or 32 bits of the rS register, that is:
8-bit wdata = rS[24:31]
16-bit wdata = rS[16:31]
32-bit wdata = rS[ 0:31]
Likewise, read data is loaded into the right-justified 8, 16 or 32 bits of the rT register:
8-bit rdata = rT[24:31]
16-bit rdata = rT[16:31]
32-bit rdata = rT[ 0:31]
For the byte and halfword decorated load instructions, the upper bits of the rT register are
zero filled.
The starting bit (SRTBIT) position follows the Power Architecture convention where the
MSB is bit 0 and the LSB is bit 31. The bit field width (BFW) value defines the width and
BFW = 0 specifies the maximum width, that is, the container size.
The basic decorated store includes three data transfer fields sourced from the core: the
access address (rB), the decoration (rA) and the write data (wdata) operand (rS). There are
five operations defined and most of these transactions convert a single core AHB write bus
cycle into an atomic read-modify-write, that is, an indivisible read followed by write
sequence. Support for three basic boolean logic functions (AND, OR, XOR) is provided
along with a compare-and-store operation plus a bit field insert operation. These operations
do not support any type of bit field wrapping.
In the next sections detailing the decorated store operations, the following associations
between the pseudocode variables and the core registers apply.
• decoration = rA
•
accessAddress = rB
• wdata = rS
30.3.1 Bit Field Insert (BFINS) into an 8, 16 or 32-bit Memory Container
0 1 2 3 4
bfins.b 0 0 0 0 0 0 0 SRTBIT 0 0 0
bfins.h 0 0 0 0 0 0
bfins.w 0 0 0 0 0
This command inserts a bit field defined by SRTBIT and BFW into the memory "container"
defined by the access size associated with the decorated store instruction using an atomic
read-modify-write sequence.
648/2058
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SRTBIT 0 0
SRTBIT 0
Figure 276. Decoration Format: BFINS
DocID027809 Rev 4
BFW - - - -
BFW - - - -
BFW - - - -
- - - - - - - -
- - - - - - - -
- - - - - - - -
RM0400
- - - -
- - - -
- - - -