RM0400 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Inter-
Offset 0x030
0
1
R
W w1c
w1c
Reset
0
0
16
17
R
W w1c
w1c
Reset
0
0
Figure 335. Watchdog Threshold Interrupt Status Register (WTISR)
Field
2x+1
WDGxH
[x = 0–15]
Bit 2x
WDGxL
[x = 0–15]
Note:
If num_watchdog generic parameter is zero, this register is not implemented.
36.5.1.8
Watchdog Threshold Interrupt Mask Register (WTIMR)
This register gives the interrupt mask information for the 16 possible upper and 16 possible
lower threshold limits which can be selected for each channel.
2
3
4
5
w1c
w1c
w1c
w1c
0
0
0
0
18
19
20
21
w1c
w1c
w1c
w1c
0
0
0
0
Table 378. WTISR field descriptions
This corresponds to the interrupt generated on the converted value being higher
than the programmed higher threshold as reported by WDG monitor 'x'.
0 Converted data is not higher than the programmed higher threshold.
1 Converted data is higher than the programmed higher threshold.
This corresponds to the interrupt generated on the converted value being lower than
the programmed lower threshold as reported by WDG monitor 'x'.
0 Converted data is not lower than the programmed lower threshold.
1 Converted data is lower than the programmed lower threshold.
DocID027809 Rev 4
6
7
8
9
w1c
w1c
w1c
w1c
0
0
0
0
22
23
24
25
w1c
w1c
w1c
w1c
0
0
0
0
Description
Access: User Read Only
10
11
12
13
w1c
w1c
w1c
w1c
0
0
0
0
26
27
28
29
w1c
w1c
w1c
w1c
0
0
0
0
14
15
w1c
w1c
0
0
30
31
w1c
w1c
0
0
777/2058
803
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