Figure 238. Pflash_Mp55 Block Diagram - STMicroelectronics SPC572L series Reference Manual

RM0400
p0_hrdata
32
Port0 haddr,
attributes
hwdata
32
IPS Interface
32
Nexus Trace haddr,
attributes
64
Flash memory controller (PFLASH Controller)

Figure 238. PFLASH_MP55 block diagram

CONTROL LOGIC
buffer hit logic
access protection
logic
addr generation
overlay remap
arbitration logic
Calibration Remap
Descriptors
DocID027809 Rev 4
Way1
Way0
Mini Cache Buffer
fl_rdata
128
On-Chip Overlay RAM
hrdata
64
PRAM backdoor
hrdata
32
fl_{rd/wr}_en
fl_addr
fl_wdata
PRAM backdoor
haddr, attributes
hwdata
On-chip Overlay RAM0
haddr, attributes
hwdata
X
B
On-chip Overlay RAM1
A
haddr, attributes
hwdata
R
64
32
64
64
557/2058
590