Deserial Serial Interface (Dsi) Configuration - STMicroelectronics SPC572L series Reference Manual

RM0400
46.5.3

Deserial Serial Interface (DSI) configuration

The DSI Configuration supports pin count reduction by serializing parallel input signals or
register bits and shifting them out in a SPI-like protocol. The timing and transfer protocol is
described in
parallel form (deserialized) and placed on the Parallel Output signals or in the DSPI_DDR.
The various features of the DSI Configuration are set in DSPI DSI Configuration Registers
(DSPI_DSICR1/0).
The DSI frames can be from 4 to 32 bits, or 64 bits when DSICR1[DSI64E] is enabled.
46.5.3.1 DSI master mode
In DSI master mode the DSPI initiates and controls the DSI transfers. The DSI master has
four different conditions (described in
can initiate a transfer:
•
Continuous.
•
Change in data.
•
Trigger signal.
•
Trigger signal combined with a change in data.
Transfer attributes are set during initialization. DSICR0[DSICTAS] field determines which of
the DSPI_CTARs will control the transfer attributes.
46.5.3.2 Slave Mode
In DSI slave mode the DSPI responds to transfers initiated by a SPI or DSI bus master. In
this mode the DSPI does not initiate DSI transfers.
Certain transfer attributes such as clock polarity and phase must be set for successful
communication with a DSI master. The DSI slave mode transfer attributes are set in the
DSPI_CTAR1.
The data is shifted out with MSB first.
46.5.3.3 DSI serialization
The DSI configuration from 4 to 64 bits can be serialized using two different sources. The
TXSS bit in the DSPI_DSICR0 selects between the DSPI DSI Serialization Data Register
(DSPI_SDR0-1) and the DSPI DSI Alternate Serialization Data Register (DSPI_ASDR0-1)
as the source of the serialized data. The DSPI_SDR0 holds the latest 32 parallel input signal
values which is sampled at every rising edge of the Bus clock.
When DSICR1[DSI64E] is enabled, 64-bit DSI Frames are supported and hence
DSPI_SDR1 holds the 32 MSB parallel input signal values which is sampled at every rising
edge of the bus clock. The DSPI_ASDR0-1 registers are written by host software and used
as an alternate source of serialized data. DSPI_ASDR1 is only usable when
DSICR1[DSI64E] is enabled.
The DSPI has to sample the (SDR/ASDR) inputs before it transmits a DSI frame. Due to the
asynchronous clocking structure within DSPI, the sampled data (from ASDR1/0 or SDR1/0)
must be synchronized into the Protocol Domain before being loaded into the Shift Register
for transmission.
Section 46.5.6: Transfer
DocID027809 Rev 4
Deserial Serial Peripheral Interface (DSPI)
formats. The received serial frames are converted to a
Section 46.5.3.5: DSI transfer initiation control) that
1185/2058
1220