Module Disable (Md) - STMicroelectronics SPC572L series Reference Manual

RM0400
45.10.3

Module disable (MD)

Module Disable mode in the SIPI is used to help reduce power consumption. By default,
SIPI is in disable mode, SIPI_MCR[MOEN] = 0, and is exited by writing
SIPI_MCR[MOEN] = 1 (see <Cross Refs>Section 45.15.1.8, SIPI Module Configuration
Register (SIPI_MCR)). Future SIPI Tx transfers are disabled in Module Disable mode. To
disable Rx functionality, the Target Enable (TEN) bit field has to be deasserted, then the
internal Rx state machine resets to initial state.
45.11 Errors
This section describes the potential errors that can occur during SIPI operation.
45.11.1 Timeout error
This error is generated at the initiator node when the acknowledge/response is not received
within the configured time in the corresponding SIPI_CTORn[TOR] field setting (see <Cross
Refs>Section 45.15.1.4, SIPI Channel Timeout Register (SIPI_CTORn)).
SIPI_ERR[TOEn] = 1 indicates that a channel timeout error has occurred (see <Cross
Refs>Section 45.15.1.13, SIPI Channel Error Register (SIPI_ERR)).
Note: SIPI should not drop the response even after timeout occurs. Software polls both error and
status flags after the transfer to see if there was a timeout error. If there was a timeout error
the response received may be discarded.
45.11.2 CRC error
A CRC error is generated at the target nodes when the CRC received with the frame does
not match with the calculated CRC. When a CRC error is detected the SIPI_SR[GCRCE] is
set (see <Cross Refs>Section 45.15.1.9, SIPI Status Register (SIPI_SR)) and an interrupt
will be generated if SIPI_MCR[CRCIE] = 1 (<Cross Refs>Section 45.15.1.8, SIPI Module
Configuration Register (SIPI_MCR)).
Note: In the case of a CRC error, the target node will not send an acknowledge to the initiator
node. Then an interrupt will be generated on the target side if the corresponding interrupt
enable bit is set. The initiator node will detect a time-out and take necessary action.
45.11.3 Maximum count reached error
This error is always generated at the target node only. The maximum count reached error is
generated when the value of the SIPI_ACR equals SIPI_MAXCR (see <Cross
Refs>Section 45.15.1.12, SIPI Address Count Register (SIPI_ACR) and <Cross
Refs>Section 45.15.1.10, SIPI Max Count Register (SIPI_MAXCR) for more details). The
SIPI_SR[MCR] will be set (see <Cross Refs>Section 45.15.1.9, SIPI Status Register
(SIPI_SR)), and an interrupt will be generated if SIPI_MCR[MCRIE] = 1 (<Cross
Refs>Section 45.15.1.8, SIPI Module Configuration Register (SIPI_MCR)).
45.11.4 Transaction ID error
This error is always generated at the initiator node only. It is generated when header bits
15–13 do not match SIPI_CSRn[TID] (transaction ID bits, see <Cross
Refs>Section 45.15.1.2, SIPI Channel Status Register (SIPI_CSRn)). The
SIPI_CSRn[TIDE] bit will be set when a TID error is detected, and an interrupt will be
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