Power Management Controller Digital Interface (Pmc_Dig) - STMicroelectronics SPC572L series Reference Manual

Power Management Controller digital interface (PMC_dig)

54 Power Management Controller digital interface
(PMC_dig)
54.1 Introduction
The power management controller (PMC) consists of two blocks: an analog block and a
digital block, which is described here.
The digital block:
•
Contains the registers and digital logic required to generate the enable signals, trim
control bits, POR reset generation and test logic for the analog block.
•
Contains the controls for PMC analog outputs to be sensed with the ADC module.
•
Contains the enable signals, trim bits, and other registers regarding the temperature
sensor.
•
Interfaces to the Reset Generation Module (MC_RGM) block, which receives the LVD
values during POR to use for phase transition conditions.
•
Has a custom interface to Flash memory via the SSCM (and DCF client blocks) which
loads the trim values during initial POR.
Caution: Do not assert the TESTPIN or the system LVDs will be deactivated.
The PMC digital block generates a transfer error event to the system if the selected address
exceeds the highest address in the PMC digital memory map, but not if an unused address
within the PMC digital memory space is accessed.
Note: The power domains measured by an LVD may not be left unpowered. They must always be
connected and in a valid operating range before the device can exit Power-on reset.
54.2 Block diagram
The block diagram for the PMC is shown in
1570/2058
Figure 935.
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