Table 1016. Itld Register Field Descriptions - STMicroelectronics SPC572L series Reference Manual

Sequence Processing Unit (SPU)
Offset 0x08
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0 0
MUX 63
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
63.5.1.1.9 Input triggers level detection control 2 (ITLD2)
Only a rising edge is detected on the outputs of the first 32 level1 Muxes and therefore
these values are not programmable. The last 32 level1 Muxes (Mux 32–63) trigger level is
programmable in the Input Triggers Level Detection Control 2 and 3 registers.
shows the format of the ITLD2 register. All of the MUX fields in the ITLD2 register have the
same description as shown in
Offset 0x0B
31 30
R
Mux47
W
Reset 0 0
15 14
R
Mux39
W
Reset 0 0
The ITLD registers Mux field is described in
Field
Mux Output Signal Detection.
00 Level is passed after synchronization (default)
Mux*
01 Posedge detection
10 Toggle detection
11 Level is passed after synchronization
63.5.1.1.10 Input triggers level detection control 3 (ITLD3)
Only a rising edge is detected on the outputs of the first 32 level1 Muxes and so these
values are not programmable. The last 32 level1 Muxes (Mux 32–63) trigger level is
programmable in the Input Triggers Level Detection Control 2 and 3 registers.
shows the format of the ITLD3 register. All of the MUX fields in the ITLD3 register have the
same description as shown in
1828/2058
0
MUX 62 MUX 61
Figure 1071. L1SEL7 register format
Table
29 28 27 26
Mux46 Mux45
0 0 0 0
13 12 11 10
Mux38 Mux37
0 0 0 0
Figure 1072. ITLD2 register format

Table 1016. ITLD register field descriptions

Table
DocID027809 Rev 4
0 0
MUX 60 MUX 59
1016.
25 24 23 22
Mux44 Mux43
0 0 0 0
9 8 7 6
Mux36 Mux35
0 0 0 0
Table 1016.
Description
1016.
Access: User read/write
8 7 6 5 4
0 0
MUX 58 MUX 57
Access: User read/write
21 20 19 18
Mux42 Mux41
0 0 0 0
5 4 3 2
Mux34 Mux33
0 0 0 0
RM0400
3 2 1 0
0
MUX 56
Figure 1072
17 16
Mux40
0 0
1 0
Mux32
0 0
Figure 1073