Table 1029. Snta0 Register Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
The SnTA0 register fields are described in
Field
0–11
Action 1 to be performed for State n true condition. The decoding of these bits is defined in
Table 1028
ACTION1
12–15 Reserved
16–27
Action 2 to be performed for State n true condition. The decoding of these bits is defined in
Table 1028
ACTION2
28–31 Reserved
63.5.1.6.2 State n true action 1 (SnTA1)
The SPU can be programmed to enable up to four different actions against a true condition
of every state. All the possible actions and their encoding are listed in
12 bits are needed to code every action. The first two actions for true condition are defined
in SnTA0 and the next two actions are defined in SnTA1.
the SnTA1 register where the state number, n = 0–7.
0x02 (State0)
0x04 (State1)
0x06 (State2)
0x08 (State3)
Offset
0x0A (State4)
0x0C(State5)
0x0E (State6)
0x10 (State7)
31 30 29 28 27
R 0 0 0 0
W
Reset 0 0 0 0 0
The SnTA1 register fields are described in
Field
0–11 Action 3 to be performed for State n true condition. The decoding of these bits is defined in
ACTION3
12–15 Reserved
16–27 Action 4 to be performed for State n true condition. The decoding of these bits is defined in
ACTION4
28–31 Reserved

Table 1029. SnTA0 register field descriptions

26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
ACTION4
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 1087. SnTA1 register format
Table 1030. SnTA1 register field descriptions
DocID027809 Rev 4
Sequence Processing Unit (SPU)
Table 1029.
Description
Figure 1087
0 0 0 0
Table 1030.
Description
Table 1028. A total of
shows the format of
Access: User read/write
8 7 6 5 4 3 2 1
ACTION3
Table 1028
Table 1028
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0
1863