Figure 560. Sipi Multiple Register Write Api - STMicroelectronics SPC572L series Reference Manual

RM0400
TC / DMA
2. Step: Set DMA & ch enable
1. Step: Write TCD
n. Step: DMA writes data
Last Step: Read Status
Interrupt generation option
For Multiple Write Transfer Request generation
1. Software will configure the Transfer Control Descriptor (TCD) of the DMA.
2. Software will write SIPI_CCRn[CHEN] = 1 and SIPI_CCRn[DAN] = 1.
3. SIPI will generate ipd_req and send it to the DMA controller.
4. SIPI will start copying data into the SIPI_CDRn through its DMA interface, depending
on the transfer count and data registers size. SIPI_CDR2[0] should be written with the
MSB.
5. When the copying process is completer, initiator SIPI will calculate CRC on header,
address and data field and start transmitting data to LFAST.
6. Software should poll the CSRn status register bits to determine if the request has
completed. If SIPI_CSRn[ACKR] = 1, an interrupt will be generated (if the
corresponding SIPI_CIRn[ACKIE] = 1).
7. If SIPI_CCRn[DEN] = 1, the SIPI request will transfer to thewill generate an ipd_req
and send it to the DMA controller. If not, the ipd_req will not be sent and the state
machine go idle.
8. Steps 4–7 will be repeated.
On Multiple Write transfer request reception
1. Target node will place the address, data and control information on its AHB Master
Interface.
2. When the process in completed, target node will generate an acknowledge frame and
send it back to the LFAST.

Figure 560. SIPI Multiple Register Write API

Channel x of SIPI Module
DocID027809 Rev 4
Serial Interprocessor Interface (SIPI)
32 bits
Multiple Write Transfer Address
Multiple Write Transfer Value
Multiple Write Transfer Count
Channel Status
Channel Error
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