Additional Debug Facilities - STMicroelectronics SPC572L series Reference Manual

e200z215An3 Core Debug Support
57.1.1.1 PowerISA 2.06 compatibility
The e200z215An3 core implements a subset of the PowerISA 2.06 internal debug features.
The following restrictions on functionality are present:
•
Instruction address compares do not support compare on physical (real) addresses.
•
Data address compares do not support compare on physical (real) addresses.
57.1.2

Additional debug facilities

In addition to the debug functionality defined in PowerISA 2.06, e200z215An3 provides
capability to link instruction and data breakpoints, provides additional instruction and data
breakpoints, extended range and value masking, multiple watchpoint outputs, provides
capability for the Performance Monitor to generate debug events, and allows for sharing of
debug resources between software and a hardware debugger. (See
debug resources by
57.1.2.1 Data trace port
The data trace port interface is provided to assist in implementing extended debug
watchpoint/breakpoint/trace capture capability with logic external to the e200z215An3 core.
This port provides information corresponding to each read or write access completed
without error by the CPU. In order to report data accesses, the Nexus 3 DTC register DI
control bit must be set to trace data accesses, not instruction accesses (i.e. the normal
setting. See the "Data Trace Control Register (DTC)" section in the Core (e200z215An3)
Nexus 3 Module chapter. The data trace port will report aligned accesses and misaligned
accesses as one access, unless the two portions of a misaligned access are non-
contiguous, such as when the second portion of the misaligned access is to address 0.
57.1.3 Hardware debug facilities
The e200z215An3 core contains facilities that allow for external test and debugging. A
modified IEEE 1149.1 control interface is used to communicate with the core resources.
This interface is implemented through a standard 1149.1 TAP (test access port) controller.
By using public instructions, the external debugger can freeze or halt the e200z215An3
core, read and write internal state and debug facilities, single-step instructions, and resume
normal execution.
Hardware Debug is enabled by setting the External Debug mode enable bit in External
Debug Control register 0 (EDBCR0
EDBCR0
are provided back to software via the settings in EDBRAC0. When the Hardware Debug
facility is enabled, software is blocked from modifying the "hardware-owned" debug
facilities. In addition, since resources are "owned" by the hardware debugger, inconsistent
values may be present if software attempts to read "hardware-owned" debug-related
resources.
When hardware debug is enabled by setting EDBCR0
resources described in
debugger. The same events described in
exceptions
running software. Hardware-owned debug events enabled in the respective DBCR0–8
registers are recorded in the EDBSR0 register (not the DBSR) regardless of MSR
debug interrupts are generated unless a) the resource is granted back to software via
1646/2058
software/hardware.) A data trace port is also provided.
overrides the Internal Debug mode enable bit DBCR0
EDM
Section 57.3, Debug registers
are also used for external debugging, but exceptions are not generated to
DocID027809 Rev 4
), which is also aliased to DBCR0
EDM
EDM
are reserved for use by the external
Section 57.2, Software debug events and
Section 57.1.4, Sharing
. Setting
EDM
unless resources
IDM
=1, the control registers and
RM0400
, and no
DE