Crossbar Switch (Xbar); Introduction; Features; Memory Map And Register Definition - STMicroelectronics SPC572L series Reference Manual

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Crossbar Switch (XBAR)

14.1

Introduction

This chapter provides information on the layout, configuration, and programming of the
crossbar switch. The crossbar switch connects bus masters and bus slaves using a
hardware interconnect matrix. This structure allows all bus masters to access different bus
slaves simultaneously with no interference while providing arbitration among the bus
masters when they access the same slave. A variety of bus arbitration methods and
attributes may be programmed on a slave-by-slave basis.
14.1.1

Features

The crossbar switch includes these distinctive features:
•
Symmetric crossbar bus switch implementation
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–
•
32-bit datapath width
•
Support for 8-, 16-, and 32-bit single transfers
•
Support for a variety of 4-, 8-, and 16-beat burst transfers including a 4-beat, 64-bit
burst for cache line accesses
•
Operation at one-to-one clock frequency with the bus masters
•
Support for low-power park mode
14.1.2

Memory map and register definition

Each slave port of the crossbar switch contains configuration registers. Read and write
transfers of the configuration registers require two bus clock cycles. The registers can only
be read from and written to in supervisor mode. Additionally, these registers can only be
read from or written to by 32-bit accesses.
A bus error response is returned if an unimplemented location is accessed within the
crossbar switch.
The slave registers also feature a bit that, when set, prevents the registers from being
written. The registers remain readable, but future write attempts have no effect on the
registers and are terminated with a bus error response to the master initiating the write. The
core, for example, takes a data storage interrupt.
Note: This section shows the registers for all eight master and slave ports. If a master or slave is
not used on this particular device, then unexpected results occur when writing to its
registers. See the Chip Configuration details for the exact master/slave assignments for
your device. Additionally, all references to the crossbar switch registers are based on the
physical port connections, not the logical port numbers.
Concurrent accesses from different masters to different slaves
Configurable slave arbitration attributes on a slave-by-slave basis
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