Table 223. Plldv Field Descriptions - STMicroelectronics SPC572L series Reference Manual

PLL Digital Interface (PLLDIG)
Field
Lock status bit. Indicates whether PLL has acquired lock.
29
0 PLL is unlocked.
LOCK
1 PLL is locked.
30 Reserved
31 Reserved
22.5.2.3 PLL Divider Register (PLLDV)
The PLLDV register provides the PHI/PHI1 output clock reduced frequency dividers, pre-
divider, and loop divider. The values of PREDIV and MFD should not be changed when the
PLL is on and locked (working in Normal mode). If these fields are changed without
powering down the PLL, the PLL will lose lock and generate either a reset or an interrupt,
based on which is enabled. The reduced frequency divider fields can be modified at
anytime, but the changes only become effective after PLL is disabled, then reenabled.
Offset: 0008h
0 1
R 0
W
(1)
Reset 0 –
16 17
R 0
PREDIV
W
(1)
Reset 0 –
1. See the Clocking chapter for reset value information.
Field
0 Reserved
PHI1 reduced frequency divider. This 4-bit field determines the VCO clock post divider for driving the
PHI1 output clock.
00xx Reserved
1:4
0100 Divide by 4
RFDPHI1 0101 Divide by 5
....
1110 Divide by 14
1111 Divide by 15
5:9 Reserved
482/2058
Table 222. PLLSR field descriptions(Continued)
2 3 4 5
0
RFDPHI1
(1) (1) (1)
– – – 0
18 19 20 21
0 0
(1) (1)
– – 0 0
Figure 172. PLL Divider Register (PLLDV)

Table 223. PLLDV field descriptions

DocID027809 Rev 4
Description
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
0 0 0
(1)
0 0 0 –
Description
Access: User read/write
10 11 12 13
RFDPHI
(1) (1) (1) (1)
– – – –
26 27 28 29
MFD
(1) (1) (1) (1)
– – – –
RM0400
14 15
(1) (1)
– –
30 31
(1) (1)
– –