Table 848. Uartpto Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
Field
Reserved
0–19
Read returns 0.
Preset Timeout
20–31 PTO defines the preset value of timeout counter.
PTO[11:0] A value of 0, 1 or 2 is forbidden, otherwise the UARTSR[TO] status bit is immediately set.
Refer to the UARTCTO register.
50.4.2.24 UART Current Timeout Register (UARTCTO)
This register contains the current timeout value in UART mode, and is used in conjunction
with the UARTPTO register (see
(UARTPTO)
the reception line. UART timeout works in both CPU and DMA modes.
The timeout counter:
• Starts at zero and counts upward
•
Is clocked with LIN_CLK / (16 * LDIV) synchronized to PBRIDGEx_CLK (when ROSE
= 0)
•
Is clocked with LIN_CLK / (OSR * IBRR) synchronized to PBRIDGEx_CLK (when
ROSE = 1)
•
Is automatically enabled when UARTCR[RXEN] = 1
Note: Due to this synchronisation, UARTCTO reflects the internal counter's value (which is
clocked with LIN_CLK/16 * LDIV when ROSE = 0 or LIN_CLK/OSR * IBRR when ROSE =
1) which was present on it, before 4 to 6 clock cycles of PBRIDGEx_CLK.
It is reset when:
•
Number of frames received is equal to NEF bits
•
UARTCTO becomes equal to UARTPTO-1
•
Whenever UARTPTO is written
•
When DRF is set and DTU bit = 1
Address (GCR address)
:
0 1
R 0 0
W
Reset 0 0
16 17
R 0 0
W
Reset 0 0
1
Depends on no_of_filters. Refer to device configuration chapter to see the number of filters used in the
device.

Table 848. UARTPTO field descriptions

to monitor the number of bits received by UARTor to monitor the idle state of
1
+08h
2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
0 0
0 0 0 0
Figure 868. UART Current Timeout Register (UARTCTO)
DocID027809 Rev 4
Description
Section 50.4.2.23, UART Preset Timeout Register
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
CTO
0 0 0 0
Access: User read
10 11 12 13
0 0 0 0
0 0 0 0
26 27 28 29
0 0 0 0
LINFlexD
14 15
0 0
0 0
30 31
0 0
1491/2058
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