Functional Description - STMicroelectronics SPC572L series Reference Manual

Sigma-Delta Analog-to-Digital Converter (SDADC) Digital Interface
Field
0–15 Reserved
Software Trigger Key
This bitfield, when written with 0xFFFF, is used to generate a trigger event output which can
16–31
be used to trigger conversions of multiple SDADC blocks synchronously depending on the
ST_KEY[15:0]
SoC implementation. Any write access to this register which is different from the predefined
key is ignored. Read access will always return 0x0000.
35.6.2.9 Converted Data Register (CDR)
The Converted Data Register (CDR) stores the converted data in the data FIFO.
Offset 0x0020
0 1
R 0 0
W
Reset 0 0
16 17
R
W
Reset 0 0
The conversion result in the CDATA word is a 16-bit, signed value.
Field
0–15 Reserved
Converted Data Register
16–31
The converted datawords can be read from FIFO by reading this register. The data width is
16 bits which has actual 16-bit data (bits 15 down to 0) coming from ADC.
CDATA[15:0]
35.7

Functional description

The SDADC has four distinct available modes determined by fields in MCR.
•
Differential input mode
•
Single-ended input mode
•
External modulator mode
•
Low consumption mode
748/2058
Table 366. STKR field descriptions
2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
0 0 0 0
Figure 323. Converted Data Register (CDR)
Table 367. CDR field descriptions
DocID027809 Rev 4
Description
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
CDATA
0 0 0 0
Description
Access: User Read/Write
10 11 12 13
0 0 0 0
0 0 0 0
26 27 28 29
0 0 0 0
RM0400
14 15
0 0
0 0
30 31
0 0