Table 864. 'Functional' Reset Escalation Threshold (Rgm_Fret) Register Field Descriptions - STMicroelectronics SPC572L series Reference Manual

Reset Generation Module (MC_RGM)
Address 0x604
0
R 0
W
'Dest'
0
Reset
Figure 909. 'Functional' Reset Escalation Threshold (RGM_FRET) register

Table 864. 'Functional' Reset Escalation Threshold (RGM_FRET) register field descriptions

Field
0–3 Reserved
'Functional' Reset Escalation Threshold
4–7
If the value of this field is 0, the 'functional' reset escalation function is disabled. Any other value is
FRET the number of 'functional' resets which cause a 'destructive' reset if the RGM_FRET register isn't
written to beforehand.
51.3.1.11 External Reset Output Extension Control (RGM_EROEC) register
This register controls the assertion of the ESR0 pin after the reset sequence has completed.
Supervisor and test modes allow for read/write access, whereas read access only is allowed
in user mode. The register bit is cleared on write '1'.
Clearing the EROEC bit causes the MC_RGM to stop asserting the ESR0 pin within two 16
MHz internal RC oscillator clock cycles. The ESR0 pin cannot be asserted by writing to this
register.
This register also provides the current value sampled on ESR0 via the ERIS bit. This is
useful for software to poll if, for example, ESR0 is used in the system to synchronize the
application software with an external event.
This register is reset only on power-on.
Address 0x60C
0
R 0
W
POR 0
Figure 910. External Reset Output Extension Control (RGM_EROEC) register
1528/2058
1 2
0 0
0 0
1 2
0 0
0 0
DocID027809 Rev 4
Access: User read, Supervisor read/write, Test read/write
3 4
0
0 0
Description
Access: User read, Supervisor read/write, Test read/write
3 4
0 0
0 0
5 6
FRET
1 0
5 6
0 ERIS
0 0
RM0400
7
0
7
EROEC
w1c
1