Table 473. Gtmdi_Dpll_Wpc2 Field Descriptions - STMicroelectronics SPC572L series Reference Manual

GTM Development Interface (GTMDI)
Field
Watchpoint Trigger Output Selection 1. The WTSEL1[2:0] field selects among 8 available
watchpoint triggers which one is connected to the DPLL SASI or TASI signal. Other modules can
select this same WTSEL1 value, in this case the result trigger signal is an OR of all selected
sources.
000 SHARED_WPT[0]
30–28
001 SHARED_WPT[1]
WTSEL1 010 SHARED_WPT[2]
011 SHARED_WPT[3]
100 SHARED_WPT[4]
101 SHARED_WPT[5]
110 SHARED_WPT[6]
111 SHARED_WPT[7]
Start/Stop input signal selection 1. Selects the Start/Stop input that is used to control the watchpoint
trace messages related to DPLL SASI or TASI signals. These signals are actually a pair of signals.
21–20
00 SHARED_WPT_ST[0]
STSEL1 01 SHARED_WPT_ST[1]
10 SHARED_WPT_ST[2]
11 SHARED_WPT_ST[3]
Watchpoint Trigger Enable 1. The TEN1 field controls if a watchpoint external trigger is issued by
17 the DPLL TASI or SASI selected event.
TEN1 0 Disable External Watchpoint Trigger Generation
1 Enable External Watchpoint Trigger Generation
Start/Stop Enable 1. The SEN1 bit field enable the DPLL TASI or SASI selected event to consider
the Start/Stop inputs for watchpoint trace message generation. If this bit is cleared, the messages
16
are controlled only by JTAG writes to the WMC1 field in the GTMDI_DPLL_WPC1 register.
SEN1
0 Disable trace control from Start/Stop inputs
1 Enable trace control from Start/Stop inputs
Watchpoint Trigger Output Selection 2. The WTSEL2[2:0] field selects among 8 available
watchpoint triggers which one is connected to the DPLL RAM access signal. Other modules can
select this same WTSEL2 value, in this case the result trigger signal is an OR of all selected
sources.
000 SHARED_WPT[0]
14–12
001 SHARED_WPT[1]
WTSEL2 010 SHARED_WPT[2]
011 SHARED_WPT[3]
100 SHARED_WPT[4]
101 SHARED_WPT[5]
110 SHARED_WPT[6]
111 SHARED_WPT[7]
Start/Stop input signal selection 2. Selects the Start/Stop input that is used by the watchpoint trace
messages related to DPLL RAM access events for RAM1A, RAM1B and RAM2. These signals are
actually a pair of signals.
5–4
00 SHARED_WPT_ST[0]
STSEL2
01 SHARED_WPT_ST[1]
10 SHARED_WPT_ST[2]
11 SHARED_WPT_ST[3]
908/2058

Table 473. GTMDI_DPLL_WPC2 field descriptions

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Description
RM0400