Table 102. Instruction Storage Interrupt—Register Settings - STMicroelectronics SPC572L series Reference Manual

Core e200z215An3 description
Table 101. Data Storage Interrupt—register settings(Continued)
Register
SPV 0
WE 0
MSR CE —
EE 0
PR 0
ESR Access:
MCSR Unchanged
DEAR For Access Control exceptions, set to the effective address of the access that caused the violation.
Vector IVPR || 0x20
0:23
12.6.5.4 Instruction Storage Interrupt (offset 0x30)
An Instruction Storage interrupt (ISI) occurs when no higher priority exception exists and an
Execute Access Control exception occurs.
Table 102
Table 102. Instruction Storage Interrupt—register settings
Register
SRR0 Set to the effective address of the excepting instruction.
SRR1 Set to the contents of the MSR at the time of the interrupt
SPV 0
WE 0
MSR CE —
EE 0
PR 0
ESR VLEMI. All other bits cleared.
MCSR Unchanged
DEAR Unchanged
Vector IVPR || 0x30
0:23
12.6.5.5 External Input Interrupt (offset 0x40)
An External Input exception is signaled to the processor by the assertion of an interrupt from
the interrupt controller. The input is a level-sensitive signal expected to remain asserted until
the core acknowledges the external interrupt. If the input is negated early, recognition of the
interrupt request is not guaranteed. When the core detects the exception, if the exception is
enabled by MSR
An External Input interrupt may be delayed by other higher priority exceptions or if MSR
cleared when the exception occurs.
Table 103
276/2058
FP
ME
FE0
DE
[ST], [SPV], VLEMI. All other bits cleared.
lists register settings when an ISI is taken.
FP
ME
FE0
DE
, it takes the External Input interrupt.
EE
lists register settings when an External Input interrupt is taken.
DocID027809 Rev 4
Setting description
0
—
0
—
Setting description
0
—
0
—
FE1 0
IS 0
DS 0
PMM 0
RI —
FE1 0
IS 0
DS 0
PMM 0
RI —
RM0400
is
EE