Initialization/Application Information - STMicroelectronics SPC572L series Reference Manual

RAM controller (PRAM)
Note: The number of cycles taken for a RAM access can vary ±1 clock cycle depending on the
RAM speed relative to the RAM controller clock frequency. If system RAM is running at the
same frequency as the RAM controller, a random initial access takes 2 clock cycles. If
system RAM is running at a slower frequency, a random initial access may take 3 clock
cycles. Subsequent burst beats take either 1 or 2 cycles depending on RAM speed relative
to PRAM controller clock frequency.
27.4.1.3 Writes
Internal SRAM write operations are performed on the following byte boundaries:
•
1 byte (0:7 bits)
• 2 bytes (0:15 bits)
•
4 bytes or 1 word (0:31 bits)
If the entire 32 data bits are written to SRAM, no read operation is performed and the ECC is
calculated across the 32-bit data bus. The 7-bit ECC is appended to the data segment and
written to SRAM.
If the write operation is less than the entire 32-bit data width (1 or 2-byte segment), the
following occurs:
1. The ECC mechanism checks the entire 32-bit data bus for errors, detecting and either
correcting or flagging errors.
2. The write data bytes (1 or 2-byte segment) are merged with the corrected 32 bits on the
data bus.
3. The ECC is then calculated on the resulting 32 bits formed in the previous step.
4. The 7-bit ECC result is appended to the 32 bits from the data bus, and the 39-bit value
is then written to SRAM.
27.4.1.4 Unaligned writes
The RAM controller is compliant with the AMBA-AHB2.v6 Extensions specification with
regard to byte strobes. The size of the transfer is sufficient to cover all bytes being written
and covers more bytes in the case of an unaligned transfer. The address of the transfer is
rounded down to the nearest boundary of the size of the transaction.
It should be noted that unaligned writes always generate read-modify-write operations in the
RAM controller in order to preserve the validity of the ECC codeword.
27.4.2

Initialization/application information

To use the SRAM, the ECC must check all bits that require initialization after power on. All
writes must specify an even number of registers performed on 32-bit word-aligned
boundaries. If the write is not the entire 32-bits (8 or 16 bits), a read/modify/write operation is
generated that checks the ECC value upon the read.
To initialize the ECC, it is essential that each memory address is written to a known value
before it is read. This includes reads generated from the read-modify-write operation which
occurs when a write transfer of less than 32 bits or an unaligned write is requested. Without
writing an address to a known value first, a read from this address will most likely generate
an uncorrectable ECC event.
It is possible to initialize SRAM memory space via a stored 32-bit word instruction such as
Store Multiple Word (e_stmw) in Power Architecture VLE.
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